RISC-V

E37329

instruction set architecture open standard reduced instruction set computing architecture

RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.

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All labels observed (23)

Label	Occurrences
RISC-V canonical	29
RISC-V architecture	5
RISC-V instruction set architecture	5
RISC-V ISA	2
RISC-V base integer ISA	2
RV32I	2
RV64I	2
RISC-V 128-bit integer ISA	1
RISC-V 64-bit integer ISA	1
RISC-V C compressed extension	1
RISC-V I base integer extension	1
RISC-V ISA specification	1
RISC-V ISA specifications	1
RISC-V SoCs	1
RISC-V base and standard extensions	1
RISC-V base integer ISA RV128I	1
RISC-V base integer ISA RV32I	1
RISC-V base integer extension I	1
RISC-V floating-point extensions	1
RISC-V microcontrollers	1
RISC-V modular extension scheme	1
RISC-V privileged architecture specifications	1
Zifencei (instruction-fetch fence)	1

How this entity was disambiguated

This entity first appeared as the object of triple T286868 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.

NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07

Target entity: RISC-V
Context triple: [Linux, supportsArchitecture, RISC-V]

A. ARM
ARM is a family of energy-efficient RISC processor architectures widely used in mobile devices, embedded systems, and increasingly in laptops and servers.
B. UCSD p-System
UCSD p-System is a portable operating system and programming environment based on the Pascal language and p-code virtual machine, widely used in the late 1970s and early 1980s across multiple hardware platforms.
C. Rust
Rust is a modern systems programming language focused on memory safety, concurrency, and performance without a garbage collector.
D. Intel Arc
Intel Arc is a line of discrete graphics processing units (GPUs) developed by Intel for gaming, content creation, and high-performance graphics workloads.
E. Ada (programming language)
Ada is a statically typed, high-level programming language designed with strong support for reliability, safety, and real-time systems, widely used in mission-critical and embedded applications such as aerospace and defense.
F. None of above. chosen
G. Unsure - the case is ambiguous/there is not enough information to decide.

NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07

Target entity: RISC-V
Target entity description: RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.

A. ARM
ARM is a family of energy-efficient RISC processor architectures widely used in mobile devices, embedded systems, and increasingly in laptops and servers.
B. UCSD p-System
UCSD p-System is a portable operating system and programming environment based on the Pascal language and p-code virtual machine, widely used in the late 1970s and early 1980s across multiple hardware platforms.
C. Rust
Rust is a modern systems programming language focused on memory safety, concurrency, and performance without a garbage collector.
D. Intel Arc
Intel Arc is a line of discrete graphics processing units (GPUs) developed by Intel for gaming, content creation, and high-performance graphics workloads.
E. Ada (programming language)
Ada is a statically typed, high-level programming language designed with strong support for reliability, safety, and real-time systems, widely used in mission-critical and embedded applications such as aerospace and defense.
F. None of above. chosen

Statements (78)

Predicate	Object
instanceOf	instruction set architecture ⓘ open standard ⓘ reduced instruction set computing architecture ⓘ
allows	custom extensions ⓘ proprietary extensions ⓘ
basedOn	RISC principles ⓘ
competesWith	ARM architecture ⓘ linked to: Acorn RISC Machine MIPS architecture ⓘ linked to: MIPS x86 architecture ⓘ linked to: x86
countryOfOrigin	United States ⓘ linked to: United States of America
designedFor	embedded systems ⓘ general-purpose computing ⓘ research ⓘ
developedBy	UC Berkeley ASPIRE Lab ⓘ UC Berkeley Parallel Computing Laboratory ⓘ
governedBy	RISC-V International ⓘ
hasBaseISA	RV128I ⓘ RV32I ⓘ linked to: RISC-V RV64I ⓘ linked to: RISC-V
hasBinaryFormat	ELF ⓘ
hasDebugSupport	OpenOCD for RISC-V ⓘ
hasDesignGoal	energy efficiency ⓘ long-term stability of base ISA ⓘ scalability ⓘ simplicity ⓘ
hasEcosystem	open-source hardware implementations ⓘ open-source software toolchains ⓘ
hasEndianness	little-endian (primary) ⓘ
hasExtension	A (atomic instructions) ⓘ B (bit-manipulation extension) ⓘ C (compressed instructions) ⓘ D (double-precision floating point) ⓘ F (single-precision floating point) ⓘ H (hypervisor extension) ⓘ K (cryptography extensions) ⓘ M (integer multiplication and division) ⓘ P (packed-SIMD extension) ⓘ V (vector extension) ⓘ Zicsr (control and status register instructions) ⓘ Zifencei (instruction-fetch fence) ⓘ linked to: RISC-V
hasLicenseModel	open and non-restrictive license ⓘ
hasProperty	extensible ⓘ free to use ⓘ modular ⓘ open ⓘ royalty-free ⓘ
hasSimulator	QEMU RISC-V target ⓘ Spike RISC-V ISA simulator ⓘ
hasSpecification	debug specification ⓘ privileged architecture specification ⓘ unprivileged ISA specification ⓘ vector extension specification ⓘ
hasToolchain	GCC for RISC-V ⓘ linked to: GNU Compiler Collection LLVM/Clang for RISC-V ⓘ linked to: LLVM
inspiredBy	Berkeley RISC projects ⓘ MIPS architecture ⓘ linked to: MIPS SPARC ⓘ linked to: SPARC microprocessor architecture
originatedAt	University of California, Berkeley ⓘ
previouslyGovernedBy	RISC-V Foundation ⓘ linked to: RISC-V International
supportsAddressWidth	128-bit ⓘ 32-bit ⓘ 64-bit ⓘ
supportsOperatingSystem	FreeBSD ⓘ Linux ⓘ NetBSD ⓘ OpenBSD ⓘ RT-Thread ⓘ Zephyr RTOS ⓘ
supportsPrivilegeLevel	hypervisor mode (H) ⓘ machine mode (M) ⓘ supervisor mode (S) ⓘ user mode (U) ⓘ
usedIn	IoT devices ⓘ Linux-capable processors ⓘ accelerators ⓘ edge computing devices ⓘ microcontrollers ⓘ system-on-chips ⓘ

How these facts were elicited

Referenced by (63)

Full triples — surface form annotated when it differs from this entity's canonical label.

Linux → supportsArchitecture → RISC-V ⓘ

GNU Compiler Collection → supportsArchitecture → RISC-V ⓘ

GNU Debugger → supportsArchitecture → RISC-V ⓘ

MicroPython → targetPlatform → RISC-V microcontrollers ⓘ

linked to: RISC-V

RISC-V → hasBaseISA → RV32I ⓘ

linked to: RISC-V

RISC-V → hasBaseISA → RV64I ⓘ

linked to: RISC-V

RISC-V → hasExtension → Zifencei (instruction-fetch fence) ⓘ

linked to: RISC-V

MIPS → influenced → RISC-V ⓘ

Gentoo Linux → supportsPlatform → RISC-V ⓘ

OpenWrt → supportsPlatform → RISC-V ⓘ

Clang → targetArchitecture → RISC-V ⓘ

LLVM → supportsArchitecture → RISC-V ⓘ

GDB → supportsArchitecture → RISC-V ⓘ

GNU C Library → supportsArchitecture → RISC-V ⓘ

FreeBSD → architectureSupport → RISC-V ⓘ

Zig → supportsArchitecture → RISC-V ⓘ

FreeRTOS → platform → RISC-V ⓘ

NetBSD → supports → RISC-V architecture ⓘ

linked to: RISC-V

David A. Patterson → helpedDevelop → RISC-V instruction set architecture ⓘ

linked to: RISC-V

RISC-V International → oversees → RISC-V instruction set architecture ⓘ

linked to: RISC-V

RISC-V International → standardizes → RISC-V instruction set architecture ⓘ

linked to: RISC-V

RISC-V International → promotes → RISC-V instruction set architecture ⓘ

linked to: RISC-V

RISC-V International → governsStandard → RISC-V privileged architecture specifications ⓘ

linked to: RISC-V

UC Berkeley Parallel Computing Laboratory → researchArea → RISC-V ⓘ

UC Berkeley Parallel Computing Laboratory → uses → RISC-V instruction set architecture ⓘ

linked to: RISC-V

RV128I → architectureFamily → RISC-V ⓘ

RV128I → compatibleWith → RISC-V modular extension scheme ⓘ

linked to: RISC-V

RV128I → relatedTo → RV32I ⓘ

linked to: RISC-V

RV128I → relatedTo → RV64I ⓘ

linked to: RISC-V

A (atomic instructions) → partOf → RISC-V ISA ⓘ

linked to: RISC-V

A (atomic instructions) → compatibleWith → RISC-V base integer ISA RV32I ⓘ

linked to: RISC-V

A (atomic instructions) → compatibleWith → RISC-V base integer ISA RV128I ⓘ

linked to: RISC-V

A (atomic instructions) → belongsToCategory → RISC-V base and standard extensions ⓘ

linked to: RISC-V

V (vector extension) → partOf → RISC-V ISA ⓘ

linked to: RISC-V

V (vector extension) → compatibleWith → RISC-V base integer ISA ⓘ

linked to: RISC-V

V (vector extension) → compatibleWith → RISC-V floating-point extensions ⓘ

linked to: RISC-V

B (bit-manipulation extension) → architecture → RISC-V ⓘ

B (bit-manipulation extension) → appliesTo → RISC-V 64-bit integer ISA ⓘ

linked to: RISC-V

B (bit-manipulation extension) → appliesTo → RISC-V 128-bit integer ISA ⓘ

linked to: RISC-V

B (bit-manipulation extension) → compatibleWith → RISC-V base integer extension I ⓘ

linked to: RISC-V

P (packed-SIMD extension) → architectureFamily → RISC-V ⓘ

P (packed-SIMD extension) → compatibleWith → RISC-V base integer ISA ⓘ

linked to: RISC-V

Zephyr RTOS → supports → RISC-V architecture ⓘ

linked to: RISC-V

RT-Thread → supportsArchitecture → RISC-V ⓘ

Spike RISC-V ISA simulator → supportsArchitecture → RISC-V ⓘ

Spike RISC-V ISA simulator → conformsTo → RISC-V ISA specification ⓘ

linked to: RISC-V

QEMU RISC-V target → supportsArchitecture → RISC-V ⓘ

QEMU RISC-V target → supportsISAExtension → RISC-V I base integer extension ⓘ

linked to: RISC-V

QEMU RISC-V target → supportsISAExtension → RISC-V C compressed extension ⓘ

linked to: RISC-V

OpenOCD for RISC-V → supportsArchitecture → RISC-V ⓘ

All labels observed (23)

How this entity was disambiguated Show

Statements (78)

How these facts were elicited Show

Referenced by (63)

How this entity was disambiguated

How these facts were elicited