QEMU RISC-V target

E193755

QEMU target architecture backend RISC-V emulator

QEMU RISC-V target is an emulation backend in the QEMU virtualization platform that allows users to run and test RISC-V software on non-RISC-V host systems.

Try in SPARQL Jump to: Surface forms Disambiguation Statements Elicitation Referenced by

All labels observed (3)

Label	Occurrences
QEMU RISC-V maintainers	1
QEMU RISC-V target canonical	1
qemu-system-riscv64	1

How this entity was disambiguated

This entity first appeared as the object of triple T1717942 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.

NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07

Target entity: QEMU RISC-V target
Context triple: [RISC-V, hasSimulator, QEMU RISC-V target]

A. RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
B. MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
C. Bytecode Alliance
Bytecode Alliance is a nonprofit industry consortium focused on advancing secure, modular, and portable software through technologies built around WebAssembly.
D. Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
E. Calliope mini
Calliope mini is a small educational microcontroller board designed to teach children and beginners programming and electronics through interactive projects.
F. None of above. chosen
G. Unsure - the case is ambiguous/there is not enough information to decide.

NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07

Target entity: QEMU RISC-V target
Target entity description: QEMU RISC-V target is an emulation backend in the QEMU virtualization platform that allows users to run and test RISC-V software on non-RISC-V host systems.

A. RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
B. MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
C. Bytecode Alliance
Bytecode Alliance is a nonprofit industry consortium focused on advancing secure, modular, and portable software through technologies built around WebAssembly.
D. Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
E. Calliope mini
Calliope mini is a small educational microcontroller board designed to teach children and beginners programming and electronics through interactive projects.
F. None of above. chosen

Statements (54)

Predicate	Object
instanceOf	QEMU target architecture backend ⓘ RISC-V emulator ⓘ
configurationOption	--target-list=riscv32-linux-user ⓘ --target-list=riscv32-softmmu ⓘ --target-list=riscv64-linux-user ⓘ --target-list=riscv64-softmmu ⓘ
hostPlatform	aarch64 ⓘ other non-RISC-V architectures ⓘ x86_64 ⓘ
implementedInLanguage	C ⓘ
introducedIn	QEMU 2.x era ⓘ
license	GNU General Public License version 2 ⓘ linked to: GNU General Public License
maintainedBy	QEMU RISC-V maintainers ⓘ linked to: QEMU RISC-V target
partOf	QEMU ⓘ
repository	QEMU upstream git repository ⓘ
supportsArchitecture	RISC-V ⓘ
supportsBoardModel	sifive_e board ⓘ linked to: sifive_u board sifive_u board ⓘ spike-like machine model ⓘ virt board ⓘ
supportsCPUModel	SiFive E-series CPU models ⓘ linked to: SiFive SiFive U-series CPU models ⓘ linked to: SiFive generic RISC-V CPU ⓘ rv32 virtual CPU models ⓘ rv64 virtual CPU models ⓘ
supportsDebugging	GDB remote debugging ⓘ
supportsExecutionType	system emulation ⓘ user-mode emulation ⓘ
supportsFeature	RISC-V CSR emulation ⓘ RISC-V MMU emulation ⓘ RISC-V interrupt controller emulation ⓘ RISC-V page-based virtual memory ⓘ RISC-V timer emulation ⓘ device tree based machine description ⓘ
supportsGuestOS	BSD variants ⓘ Linux ⓘ bare-metal RISC-V firmware ⓘ
supportsISA	RV32 ⓘ RV64 ⓘ
supportsISAExtension	RISC-V A atomic extension ⓘ RISC-V C compressed extension ⓘ linked to: RISC-V RISC-V D double-precision floating-point extension ⓘ RISC-V F single-precision floating-point extension ⓘ RISC-V I base integer extension ⓘ linked to: RISC-V RISC-V M integer multiplication and division extension ⓘ RISC-V privileged architecture ⓘ
supportsMode	machine mode ⓘ supervisor mode ⓘ user mode ⓘ
usedFor	RISC-V application testing ⓘ RISC-V firmware development ⓘ RISC-V operating system development ⓘ continuous integration for RISC-V projects ⓘ running RISC-V software on non-RISC-V hosts ⓘ

How these facts were elicited

Referenced by (3)

Full triples — surface form annotated when it differs from this entity's canonical label.

RISC-V → hasSimulator → QEMU RISC-V target ⓘ

QEMU RISC-V target → maintainedBy → QEMU RISC-V maintainers ⓘ

linked to: QEMU RISC-V target

sifive_u board → emulatedByCommand → qemu-system-riscv64 ⓘ