Disambiguation evidence for RISC-V via surface form

"RISC-V"

Triples (44)

Triples where some other subject referred to this entity as "RISC-V".

Linux → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
GNU Compiler Collection → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
GNU Debugger → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
MIPS → influenced →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Gentoo Linux → supportsPlatform →
"RISC-V"
↳ resolves to RISC-V
ⓘ
OpenWrt → supportsPlatform →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Clang → targetArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
LLVM → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
GDB → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
GNU C Library → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
FreeBSD → architectureSupport →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Zig → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
FreeRTOS → platform →
"RISC-V"
↳ resolves to RISC-V
ⓘ
UC Berkeley Parallel Computing Laboratory → researchArea →
"RISC-V"
↳ resolves to RISC-V
ⓘ
RV128I → architectureFamily →
"RISC-V"
↳ resolves to RISC-V
ⓘ
B (bit-manipulation extension) → architecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
P (packed-SIMD extension) → architectureFamily →
"RISC-V"
↳ resolves to RISC-V
ⓘ
RT-Thread → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Spike RISC-V ISA simulator → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
QEMU RISC-V target → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
OpenOCD for RISC-V → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Microprocessor without Interlocked Pipeline Stages → influenced →
"RISC-V"
↳ resolves to RISC-V
ⓘ
QEMU → supportsGuestArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
GNU NYU Ada Translator → supportsTarget →
"RISC-V"
↳ resolves to RISC-V
ⓘ
GNU/Linux → platform →
"RISC-V"
↳ resolves to RISC-V
ⓘ
LLD → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
linked to: LLD linker
compiler-rt → target →
"RISC-V"
↳ resolves to RISC-V
ⓘ
musl → targetArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
GNU As → supportsTarget →
"RISC-V"
↳ resolves to RISC-V
ⓘ
SiFive → architectureUsed →
"RISC-V"
↳ resolves to RISC-V
ⓘ
IAR Embedded Workbench → supportsArchitectureFamily →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Cranelift → supportsISA →
"RISC-V"
↳ resolves to RISC-V
ⓘ
linked to: Cranelift code generator (as part of Wasmtime ecosystem)
Krste Asanović → fieldOfWork →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Zbr (bit matrix operations) → architectureStyle →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Zbt (ternary bit-manipulation) → architectureDomain →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Zephyr → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
sifive_u board → architecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Quick EMUlator → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
TCG (Tiny Code Generator) → supportsGuestArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Spike → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
U-Boot → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
PaddlePaddle → supportsHardware →
"RISC-V"
↳ resolves to RISC-V
ⓘ
seL4 microkernel → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ
Buildroot → supportsArchitecture →
"RISC-V"
↳ resolves to RISC-V
ⓘ