P (packed-SIMD extension)
E193751
P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
All labels observed (1)
| Label | Occurrences |
|---|---|
| P (packed-SIMD extension) canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T1717918 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: P (packed-SIMD extension) Context triple: [RISC-V, hasExtension, P (packed-SIMD extension)]
-
A.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
B.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
C.
SSSE3
SSSE3 (Supplemental Streaming SIMD Extensions 3) is an Intel SIMD instruction set extension that enhances performance for multimedia, signal processing, and other parallelizable workloads.
-
D.
SSE2
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: P (packed-SIMD extension) Target entity description: P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
-
A.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
B.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
C.
SSSE3
SSSE3 (Supplemental Streaming SIMD Extensions 3) is an Intel SIMD instruction set extension that enhances performance for multimedia, signal processing, and other parallelizable workloads.
-
D.
SSE2
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
Statements (39)
| Predicate | Object |
|---|---|
| instanceOf |
RISC-V instruction set extension
ⓘ
SIMD instruction set extension ⓘ |
| abbreviation | P ⓘ |
| architectureFamily | RISC-V ⓘ |
| category | RISC-V standard extension (proposed/working-group level) ⓘ |
| compatibleWith |
RISC-V base integer ISA
ⓘ
linked to:
RISC-V
|
| dataParallelismModel | packed data parallelism ⓘ |
| designedFor | RISC-V integer cores ⓘ |
| fullName | Packed-SIMD extension for RISC-V ⓘ |
| goal |
improve performance of embedded DSP applications
ⓘ
reduce instruction count for data-parallel kernels ⓘ |
| granularity | sub-word packed elements in general-purpose registers ⓘ |
| improves |
energy efficiency for parallel data processing
ⓘ
throughput of vectorizable operations ⓘ |
| intendedDomain |
embedded systems
ⓘ
low-power processors ⓘ real-time signal processing systems ⓘ |
| operationType |
bitwise packed operations
ⓘ
fixed-point SIMD operations ⓘ integer SIMD operations ⓘ packed add and subtract operations ⓘ packed comparison operations ⓘ packed multiply operations ⓘ packed shift operations ⓘ saturating arithmetic operations ⓘ |
| purpose | accelerate parallel data processing tasks ⓘ |
| relatedConcept |
RISC-V V (vector) extension
ⓘ
linked to:
V (vector extension)
SIMD within a register (SWAR) ⓘ packed-SIMD instructions in other ISAs ⓘ |
| supports | packed single-instruction multiple-data operations ⓘ |
| targetWorkloads |
DSP-style workloads
ⓘ
embedded media processing ⓘ multimedia workloads ⓘ signal processing ⓘ |
| useCase |
audio processing
ⓘ
communications signal processing ⓘ image processing ⓘ software-defined radio ⓘ video processing ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: P (packed-SIMD extension) Description of subject: P (packed-SIMD extension) is a RISC-V instruction set extension that adds packed single-instruction multiple-data operations to accelerate parallel data processing tasks such as signal processing and multimedia workloads.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.