V (vector extension)

E193749

RISC-V extension vector instruction set architecture

V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.

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All labels observed (5)

Label	Occurrences
RISC-V ISA extensions	1
RISC-V V (vector) extension	1
RISC-V V extension	1
RISC-V Vector Extension	1
V (vector extension) canonical	1

How this entity was disambiguated

This entity first appeared as the object of triple T1717914 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.

NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07

Target entity: V (vector extension)
Context triple: [RISC-V, hasExtension, V (vector extension)]

A. Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
B. Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
C. SSE2
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
D. VMX
VMX is a vector processing extension to the PowerPC architecture designed to accelerate multimedia, signal processing, and other parallelizable computations.
E. AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
F. None of above. chosen
G. Unsure - the case is ambiguous/there is not enough information to decide.

NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07

Target entity: V (vector extension)
Target entity description: V (vector extension) is the RISC-V standard for scalable vector processing, enabling efficient parallel computation on variable-length data vectors.

A. Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
B. Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
C. SSE2
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
D. VMX
VMX is a vector processing extension to the PowerPC architecture designed to accelerate multimedia, signal processing, and other parallelizable computations.
E. AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
F. None of above. chosen

Statements (49)

Predicate	Object
instanceOf	RISC-V extension ⓘ vector instruction set architecture ⓘ
alsoKnownAs	RISC-V V extension ⓘ linked to: V (vector extension) RISC-V Vector Extension ⓘ linked to: V (vector extension)
architectureStyle	scalable vector architecture ⓘ
compatibleWith	RISC-V base integer ISA ⓘ linked to: RISC-V RISC-V floating-point extensions ⓘ linked to: RISC-V
definedBy	RISC-V International ⓘ
designGoal	energy-efficient parallel computation ⓘ performance portability ⓘ scalability across microarchitectures ⓘ support for a wide range of vector lengths ⓘ
enables	efficient utilization of vector hardware resources ⓘ hardware-agnostic vectorized code ⓘ parallel computation on variable-length data vectors ⓘ
hasProperty	decoupling of software vector length from hardware width ⓘ implementation-defined maximum vector length ⓘ support for both 32-bit and 64-bit base ISAs ⓘ support for different element sizes ⓘ support for mixed-precision operations ⓘ
keyConcept	mask registers ⓘ vector configuration instructions ⓘ vector register grouping ⓘ vector-length-agnostic programming model ⓘ
partOf	RISC-V ISA ⓘ linked to: RISC-V
supports	SIMD-like computation ⓘ data-level parallelism ⓘ fixed-point vector operations ⓘ floating-point vector operations ⓘ integer vector operations ⓘ predicated execution ⓘ segmented vector operations ⓘ tail-agnostic execution ⓘ tail-undisturbed execution ⓘ variable-length vectors ⓘ vector arithmetic operations ⓘ vector load and store operations ⓘ vector mask operations ⓘ vector permutation operations ⓘ vector processing ⓘ vector reduction operations ⓘ vector registers ⓘ vectorized loops ⓘ
usedFor	data analytics ⓘ high-performance computing ⓘ image processing ⓘ machine learning workloads ⓘ scientific computing ⓘ signal processing ⓘ

How these facts were elicited

Referenced by (5)

Full triples — surface form annotated when it differs from this entity's canonical label.

RISC-V → hasExtension → V (vector extension) ⓘ

RISC-V International → governsStandard → RISC-V ISA extensions ⓘ

linked to: V (vector extension)

V (vector extension) → alsoKnownAs → RISC-V V extension ⓘ

linked to: V (vector extension)

V (vector extension) → alsoKnownAs → RISC-V Vector Extension ⓘ

linked to: V (vector extension)

P (packed-SIMD extension) → relatedConcept → RISC-V V (vector) extension ⓘ

linked to: V (vector extension)

All labels observed (5)

How this entity was disambiguated Show

Statements (49)

How these facts were elicited Show

Referenced by (5)

How this entity was disambiguated

How these facts were elicited