Spike RISC-V ISA simulator
E193754
Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
All labels observed (1)
| Label | Occurrences |
|---|---|
| Spike RISC-V ISA simulator canonical | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T1717941 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Spike RISC-V ISA simulator Context triple: [RISC-V, hasSimulator, Spike RISC-V ISA simulator]
-
A.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
SPIM
SPIM was the former ICAO airport code for Jorge Chávez International Airport in Lima, Peru, before it was changed to SPJC.
-
C.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
D.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
E.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: Spike RISC-V ISA simulator Target entity description: Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
-
A.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
B.
SPIM
SPIM was the former ICAO airport code for Jorge Chávez International Airport in Lima, Peru, before it was changed to SPJC.
-
C.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
D.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
E.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
- F. None of above. chosen
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
RISC-V ISA simulator
ⓘ
instruction set simulator ⓘ reference implementation ⓘ software tool ⓘ |
| category |
computer architecture tool
ⓘ
processor simulator ⓘ |
| conformsTo |
RISC-V ISA specification
ⓘ
linked to:
RISC-V
|
| developer |
RISC-V community
ⓘ
contributors from RISC-V ecosystem ⓘ |
| domain |
computer architecture
ⓘ
embedded systems ⓘ processor design ⓘ |
| executionModel | software emulation of RISC-V instructions ⓘ |
| feature |
command-line interface
ⓘ
configuration of RISC-V core parameters ⓘ debugging support ⓘ instruction-accurate simulation ⓘ support for different RISC-V privilege levels ⓘ support for multiple RISC-V extensions ⓘ |
| input |
RISC-V ELF executables
ⓘ
RISC-V binaries ⓘ |
| license | open source license ⓘ |
| name | Spike ⓘ |
| output |
architectural state traces
ⓘ
simulated program behavior ⓘ |
| programmingLanguage | C++ ⓘ |
| relatedTo |
RISC-V Foundation
ⓘ
linked to:
RISC-V International
RISC-V International ⓘ |
| role | official reference software simulator for the RISC-V ISA ⓘ |
| shortName | Spike ⓘ |
| simulates |
RISC-V cores
ⓘ
RISC-V instructions ⓘ RISC-V memory model behavior ⓘ RISC-V privilege modes ⓘ |
| supportsArchitecture | RISC-V ⓘ |
| targetUser |
RISC-V hardware designers
ⓘ
RISC-V researchers ⓘ RISC-V software developers ⓘ |
| typicalUseCase |
early-stage RISC-V CPU design validation
ⓘ
software bring-up before RISC-V silicon is available ⓘ |
| use |
ISA compliance checking
ⓘ
functional simulation of RISC-V programs ⓘ testing of RISC-V implementations ⓘ validation of RISC-V implementations ⓘ |
| usedFor |
conformance testing against RISC-V specifications
ⓘ
reference for RISC-V hardware implementations ⓘ reference for other RISC-V simulators ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: Spike RISC-V ISA simulator Description of subject: Spike RISC-V ISA simulator is the official reference software simulator for the RISC-V instruction set architecture, used to validate and test RISC-V implementations.
Referenced by (1)
Full triples — surface form annotated when it differs from this entity's canonical label.