Microprocessor without Interlocked Pipeline Stages

E193757

Microprocessor without Interlocked Pipeline Stages (MIPS) is a RISC microprocessor architecture known for its simple, efficient design and widespread use in embedded systems, workstations, and educational settings.

All labels observed (2)

How this entity was disambiguated

Statements (59)

Predicate Object
instanceOf RISC architecture ⓘ
instruction set architecture ⓘ
abbreviation MIPS ⓘ
countryOfOrigin United States ⓘ
designedBy MIPS Computer Systems ⓘ
linked to: MIPS
designPhilosophy reduced instruction set computing ⓘ
endianness big-endian ⓘ
little-endian ⓘ
firstCommercialImplementation R2000 ⓘ
followedByImplementation R3000 ⓘ
R4000 ⓘ
fullName Microprocessor without Interlocked Pipeline Stages ⓘ
hasCallingConvention n32 ABI ⓘ
n64 ABI ⓘ
o32 ABI ⓘ
hasExtension MIPS DSP extensions ⓘ
linked to: MIPS

MIPS MT (multithreading) ⓘ
linked to: MIPS

MIPS SIMD extensions ⓘ
MIPS16 ⓘ
linked to: MIPS
hasFeature delayed branch ⓘ
delayed load ⓘ
fixed-length instructions ⓘ
load-store architecture ⓘ
pipelined execution ⓘ
register-based operations ⓘ
separate integer and floating-point register files ⓘ
simple instruction decoding ⓘ
hasVariant MIPS I ⓘ
linked to: MIPS

MIPS II ⓘ
MIPS III ⓘ
MIPS IV ⓘ
MIPS V ⓘ
MIPS32 ⓘ
linked to: MIPS

MIPS64 ⓘ
linked to: MIPS
influenced ARM architecture ⓘ
linked to: ARM

RISC-V ⓘ
SPARC ⓘ
influencedBy Berkeley RISC ⓘ
RISC I ⓘ
introducedInDecade 1980s ⓘ
notableUse Nintendo 64 ⓘ
Sony PlayStation ⓘ
linked to: PlayStation
pipelineStages execute ⓘ
instruction decode ⓘ
instruction fetch ⓘ
memory access ⓘ
write back ⓘ
registerCount 32 general-purpose registers ⓘ
typicalPipelineDepth 5 stages ⓘ
usedIn consumer electronics ⓘ
educational platforms ⓘ
embedded systems ⓘ
game consoles ⓘ
networking equipment ⓘ
routers ⓘ
workstations ⓘ
usedInEducationFor compiler design courses ⓘ
computer architecture courses ⓘ
wordSize 32-bit ⓘ

How these facts were elicited

Referenced by (4)

Full triples — surface form annotated when it differs from this entity's canonical label.

MIPS → fullName → Microprocessor without Interlocked Pipeline Stages ⓘ
MIPS → abbreviationFor → Microprocessor without Interlocked Pipeline Stages ⓘ
SPARC → fullName → Scalable Processor Architecture ⓘ
linked to: Microprocessor without Interlocked Pipeline Stages
Microprocessor without Interlocked Pipeline Stages → fullName → Microprocessor without Interlocked Pipeline Stages ⓘ