RISC I
E339011
RISC I is an early experimental reduced instruction set computer (RISC) processor design developed at UC Berkeley that helped pioneer and popularize the RISC architecture approach.
All labels observed (2)
| Label | Occurrences |
|---|---|
| RISC I canonical | 3 |
| RISC I microprocessor | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T3244623 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RISC I Context triple: [SPARC, influencedBy, RISC I]
-
A.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
B.
RCA 1802 microprocessor
The RCA 1802 microprocessor is an early CMOS-based 8-bit CPU notable for its low power consumption, radiation hardness, and use in spacecraft and embedded systems in the 1970s and 1980s.
-
C.
Crusoe microprocessor
The Crusoe microprocessor is a low-power, x86-compatible CPU line from Transmeta that used code-morphing software to translate x86 instructions to an underlying VLIW architecture, targeting laptops and mobile devices.
-
D.
RISC architecture
RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
-
E.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: RISC I Target entity description: RISC I is an early experimental reduced instruction set computer (RISC) processor design developed at UC Berkeley that helped pioneer and popularize the RISC architecture approach.
-
A.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
B.
RCA 1802 microprocessor
The RCA 1802 microprocessor is an early CMOS-based 8-bit CPU notable for its low power consumption, radiation hardness, and use in spacecraft and embedded systems in the 1970s and 1980s.
-
C.
Crusoe microprocessor
The Crusoe microprocessor is a low-power, x86-compatible CPU line from Transmeta that used code-morphing software to translate x86 instructions to an underlying VLIW architecture, targeting laptops and mobile devices.
-
D.
RISC architecture
RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
-
E.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
- F. None of above. chosen
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
RISC processor design
ⓘ
experimental processor ⓘ microprocessor architecture ⓘ |
| academicAdvisor | David A. Patterson ⓘ |
| academicInstitution | University of California, Berkeley ⓘ |
| architectureFamily |
RISC
ⓘ
linked to:
RISC architecture
|
| basedOn | reduced instruction set computing principles ⓘ |
| category |
Berkeley RISC project processors
ⓘ
linked to:
Berkeley RISC projects
RISC microprocessors ⓘ experimental microprocessors ⓘ |
| clockFrequency | about 1 MHz ⓘ |
| countryOfOrigin |
United States
ⓘ
linked to:
United States of America
|
| demonstrated | that simpler instruction sets can yield higher performance ⓘ |
| designedFor |
performance evaluation of RISC concepts
ⓘ
research ⓘ |
| developer |
UC Berkeley Computer Science Division
ⓘ
University of California, Berkeley ⓘ |
| dieSize | approximately 77 mm^2 ⓘ |
| fabricationTechnology | NMOS ⓘ |
| field |
computer architecture
ⓘ
microprocessor design ⓘ |
| impact | popularized RISC design in academia and industry ⓘ |
| inception |
1981
ⓘ
early 1980s ⓘ |
| influenced |
MIPS architecture
ⓘ
linked to:
MIPS
RISC II ⓘ SPARC architecture ⓘ
linked to:
SPARC microprocessor architecture
later commercial RISC processors ⓘ |
| influencedBy |
IBM 801
ⓘ
earlier CPU performance studies ⓘ |
| instructionEncoding | fixed-length ⓘ |
| instructionSetType | load-store ⓘ |
| notableFor |
helping pioneer RISC architecture approach
ⓘ
large register file ⓘ load-store architecture ⓘ pipeline-friendly design ⓘ simple fixed-length instruction set ⓘ |
| numberOfRegisters | 32 ⓘ |
| pipeline | simple instruction pipeline ⓘ |
| platform | VLSI implementation ⓘ |
| projectLeader | David A. Patterson ⓘ |
| publication |
“The Case for the Reduced Instruction Set Computer”
ⓘ
linked to:
RISC architecture
|
| publicationYear | 1980 ⓘ |
| registerWidth | 32-bit ⓘ |
| researchGroup |
Berkeley RISC project
ⓘ
linked to:
Berkeley RISC projects
|
| successor | RISC II ⓘ |
| transistorCount | approximately 44,000 transistors ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: RISC I Description of subject: RISC I is an early experimental reduced instruction set computer (RISC) processor design developed at UC Berkeley that helped pioneer and popularize the RISC architecture approach.
Referenced by (4)
Full triples — surface form annotated when it differs from this entity's canonical label.
subject linked to:
SPARC microprocessor architecture
linked to: RISC I