RISC II
E339012
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
All labels observed (3)
| Label | Occurrences |
|---|---|
| RISC II canonical | 3 |
| Berkeley RISC II | 1 |
| RISC II microprocessor | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T3244624 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RISC II Context triple: [SPARC, influencedBy, RISC II]
-
A.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
B.
Motorola 68851
The Motorola 68851 is an external paged memory management unit (MMU) designed to work with Motorola 68020 processors, providing advanced virtual memory and protection features.
-
C.
Motorola 68020 microprocessor
The Motorola 68020 microprocessor is a 32-bit CISC CPU introduced in the early 1980s that powered many workstations, servers, and Apple Macintosh computers, offering enhanced performance and features over its 68000-series predecessors.
-
D.
Motorola 68060
The Motorola 68060 is a high-performance 32-bit CISC microprocessor from Motorola’s 680x0 family, widely used in advanced Amiga systems and other computing platforms in the mid-1990s.
-
E.
Motorola 68000 family
The Motorola 68000 family is a line of 16/32-bit CISC microprocessors widely used in early personal computers, workstations, and game consoles during the 1980s and early 1990s.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: RISC II Target entity description: RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
-
A.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
B.
Motorola 68851
The Motorola 68851 is an external paged memory management unit (MMU) designed to work with Motorola 68020 processors, providing advanced virtual memory and protection features.
-
C.
Motorola 68020 microprocessor
The Motorola 68020 microprocessor is a 32-bit CISC CPU introduced in the early 1980s that powered many workstations, servers, and Apple Macintosh computers, offering enhanced performance and features over its 68000-series predecessors.
-
D.
Motorola 68060
The Motorola 68060 is a high-performance 32-bit CISC microprocessor from Motorola’s 680x0 family, widely used in advanced Amiga systems and other computing platforms in the mid-1990s.
-
E.
Motorola 68000 family
The Motorola 68000 family is a line of 16/32-bit CISC microprocessors widely used in early personal computers, workstations, and game consoles during the 1980s and early 1990s.
- F. None of above. chosen
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
RISC architecture
ⓘ
experimental processor ⓘ microprocessor ⓘ |
| academicDiscipline | computer architecture ⓘ |
| academicInstitution | University of California, Berkeley ⓘ |
| addressSpace | 32-bit ⓘ |
| architectureType | load–store architecture ⓘ |
| basedOn | RISC I ⓘ |
| branchHandling | delayed branch mechanism ⓘ |
| callStackMechanism | register windows ⓘ |
| clockFrequency | about 3 MHz ⓘ |
| completionYear | 1983 ⓘ |
| countryOfOrigin |
United States
ⓘ
linked to:
United States of America
|
| designGoal | simplified instruction set for higher performance ⓘ |
| designStartYear | early 1980s ⓘ |
| developer |
UC Berkeley Computer Science Division
ⓘ
University of California, Berkeley ⓘ |
| dieSize | about 60 mm² ⓘ |
| floatingPointSupport | via external coprocessor ⓘ |
| generalPurposeRegisters | 32 ⓘ |
| implementationTechnology | NMOS ⓘ |
| influenced |
MIPS architecture
ⓘ
linked to:
MIPS
SPARC ⓘ
linked to:
SPARC microprocessor architecture
later RISC microprocessors ⓘ |
| instructionEncoding | fixed-length 32-bit instructions ⓘ |
| instructionSetType | reduced instruction set computer ⓘ |
| microarchitectureFeature |
delayed branches
ⓘ
hardwired control ⓘ load/store architecture with register-register ALU operations ⓘ register windows for procedure calls ⓘ simple fixed-length instructions ⓘ |
| notableFor |
demonstrating performance advantages of RISC over CISC
ⓘ
influencing commercial RISC designs ⓘ |
| pipelineDepth | 3-stage pipeline ⓘ |
| pipelineStages |
execute
ⓘ
instruction decode ⓘ instruction fetch ⓘ |
| projectLeader | David A. Patterson ⓘ |
| registerFileSize | 138 registers ⓘ |
| registerWindowing | yes ⓘ |
| researchProject |
Berkeley RISC project
ⓘ
linked to:
Berkeley RISC projects
|
| supportsFloatingPointInCore | false ⓘ |
| supportsIntegerOperations | true ⓘ |
| supportsRegisterWindows | true ⓘ |
| technologyNode | 3 µm NMOS ⓘ |
| transistorCount | approximately 40,760 transistors ⓘ |
| wordSize | 32-bit ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: RISC II Description of subject: RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
Referenced by (5)
Full triples — surface form annotated when it differs from this entity's canonical label.