RISC architecture
E220200
RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
All labels observed (9)
How this entity was disambiguated
This entity first appeared as the object of triple T1936696 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: RISC architecture Context triple: [AIM alliance, relatedConcept, RISC architecture]
-
A.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
B.
Harvard architecture
Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
-
C.
POWER instruction set architecture
The POWER instruction set architecture is a reduced instruction set computing (RISC) architecture originally developed by IBM for high-performance servers and workstations, forming the basis for later PowerPC and Power Architecture designs.
-
D.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
E.
Independent Computing Architecture
Independent Computing Architecture (ICA) is Citrix's proprietary protocol for delivering virtual applications and desktops over a network, enabling remote access to centralized computing resources.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: RISC architecture Target entity description: RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
-
A.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
B.
Harvard architecture
Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
-
C.
POWER instruction set architecture
The POWER instruction set architecture is a reduced instruction set computing (RISC) architecture originally developed by IBM for high-performance servers and workstations, forming the basis for later PowerPC and Power Architecture designs.
-
D.
RISC-V
RISC-V is an open, extensible instruction set architecture (ISA) based on the reduced instruction set computing (RISC) principles, widely used for research, embedded systems, and increasingly general-purpose computing.
-
E.
Independent Computing Architecture
Independent Computing Architecture (ICA) is Citrix's proprietary protocol for delivering virtual applications and desktops over a network, enabling remote access to centralized computing resources.
- F. None of above. chosen
Statements (47)
| Predicate | Object |
|---|---|
| instanceOf |
computer architecture
ⓘ
instruction set architecture design philosophy ⓘ |
| aimsFor |
high efficiency
ⓘ
high performance ⓘ |
| benefits |
easier verification of hardware
ⓘ
lower power consumption in many designs ⓘ reduced control complexity ⓘ |
| contrastsWith | CISC architecture ⓘ |
| designGoal |
better compiler optimization
ⓘ
higher clock frequencies ⓘ one clock cycle per instruction for simple operations ⓘ simplified hardware ⓘ |
| emphasizes |
fixed-length instructions
ⓘ
hardwired control ⓘ large register file ⓘ load-store architecture ⓘ simple addressing modes ⓘ uniform instruction format ⓘ |
| focusesOn |
simple instructions
ⓘ
small instruction set ⓘ |
| hasFullForm |
Reduced Instruction Set Computer architecture
ⓘ
linked to:
RISC architecture
|
| isStandardizedIn |
RISC-V ISA specifications
ⓘ
linked to:
RISC-V
|
| isTaughtIn | computer architecture courses ⓘ |
| isUsedIn |
ARM architecture
ⓘ
Alpha architecture ⓘ MIPS architecture ⓘ
linked to:
MIPS
PowerPC architecture ⓘ
linked to:
PowerPC
RISC-V architecture ⓘ
linked to:
RISC-V
SPARC architecture ⓘ
linked to:
SPARC microprocessor architecture
|
| originatedFrom | research on efficient instruction sets ⓘ |
| popularizedIn | 1980s ⓘ |
| relatedConcept |
compiler-driven optimization
ⓘ
instruction-level parallelism ⓘ microarchitecture design ⓘ pipeline hazards ⓘ |
| supports |
out-of-order execution
ⓘ
pipelining ⓘ superscalar execution ⓘ |
| tradeOff |
more instructions per program compared to CISC
ⓘ
simpler individual instructions ⓘ |
| typicalFeature |
branch delay slots in some designs
ⓘ
memory access limited to load and store instructions ⓘ register-to-register arithmetic operations ⓘ separate instruction and data caches ⓘ |
| wasInfluencedBy |
Berkeley RISC project
ⓘ
linked to:
Berkeley RISC projects
IBM 801 project ⓘ Stanford MIPS project ⓘ
linked to:
Stanford Computer Systems Laboratory
|
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: RISC architecture Description of subject: RISC architecture is a CPU design philosophy that uses a small, highly optimized set of simple instructions to achieve high performance and efficiency.
Referenced by (39)
Full triples — surface form annotated when it differs from this entity's canonical label.
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
Berkeley RISC projects
→
notablePublication
→
"Reduced Instruction Set Computer" papers by Patterson and colleagues
ⓘ
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
subject linked to:
Acorn Archimedes in 1987
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
subject linked to:
SuperH-5 (SH-5)
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture
linked to: RISC architecture