IEEE 1149.6
E9591
IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
All labels observed (6)
| Label | Occurrences |
|---|---|
| IEEE 1149.6 canonical | 5 |
| IEEE 1149.8.1 | 2 |
| IEEE 1149.4 | 1 |
| IEEE 1149.6 AC-coupled interconnect test standard | 1 |
| IEEE Standard 1149.6 | 1 |
| IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T73264 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: IEEE 1149.6 Context triple: [IEEE 1149.1 JTAG boundary-scan standard, relatedStandard, IEEE 1149.6]
-
A.
IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
-
B.
IEEE 1532
IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
-
C.
IEEE 488 GPIB standard
The IEEE 488 GPIB standard is a widely used digital interface specification that enables communication and control among electronic test and measurement instruments and computers.
-
D.
ITU-T G.8265.1
ITU-T G.8265.1 is an international telecommunications standard that specifies the use of packet-based timing protocols over IP networks to distribute frequency synchronization, particularly for mobile and packet-based services.
-
E.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems is a peer-reviewed scholarly journal focusing on the design, analysis, and implementation of VLSI and integrated systems.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: IEEE 1149.6 Target entity description: IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
-
A.
IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
-
B.
IEEE 1532
IEEE 1532 is an extension of the JTAG boundary-scan standard that defines in-system programming and configuration procedures for programmable devices such as FPGAs and CPLDs.
-
C.
IEEE 488 GPIB standard
The IEEE 488 GPIB standard is a widely used digital interface specification that enables communication and control among electronic test and measurement instruments and computers.
-
D.
ITU-T G.8265.1
ITU-T G.8265.1 is an international telecommunications standard that specifies the use of packet-based timing protocols over IP networks to distribute frequency synchronization, particularly for mobile and packet-based services.
-
E.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems is a peer-reviewed scholarly journal focusing on the design, analysis, and implementation of VLSI and integrated systems.
- F. None of above. chosen
Statements (49)
| Predicate | Object |
|---|---|
| instanceOf |
IEEE standard
ⓘ
JTAG extension ⓘ boundary-scan test standard ⓘ |
| abbreviationOf |
IEEE Standard 1149.6
ⓘ
linked to:
IEEE 1149.6
|
| addsCapability |
testing of AC-coupled nets not testable by IEEE 1149.1 alone
ⓘ
testing of differential signaling nets not testable by IEEE 1149.1 alone ⓘ |
| appliesTo |
backplane interconnects
ⓘ
chip-to-chip differential links ⓘ high-speed serial interfaces ⓘ multi-gigabit transceiver links ⓘ |
| category |
design-for-test standard
ⓘ
testability standard ⓘ |
| defines |
AC test cells for boundary scan
ⓘ
additional boundary-scan cell types ⓘ stimulus and capture techniques for high-speed nets ⓘ test methods for AC-coupled nets ⓘ test methods for differential nets ⓘ test procedures for detecting missing AC coupling capacitors ⓘ test procedures for detecting opens and shorts on AC-coupled nets ⓘ test procedures for detecting resistive faults on high-speed nets ⓘ test procedures for detecting shorts between differential pairs ⓘ test procedures for detecting swapped differential pairs ⓘ test procedures for detecting wrong-value AC coupling capacitors ⓘ test receiver structures for AC-coupled signals ⓘ test transmitter structures for AC-coupled signals ⓘ |
| extends |
IEEE 1149.1
ⓘ
linked to:
IEEE 1149.1 JTAG boundary‑scan standard
|
| focusesOn | board-level interconnect test rather than functional test ⓘ |
| fullName |
IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks
ⓘ
linked to:
IEEE 1149.6
|
| goal |
enable structural test of AC-coupled and differential nets via JTAG
ⓘ
improve test coverage for high-speed interconnects ⓘ |
| isCompatibleWith |
IEEE 1149.1 test access port (TAP)
ⓘ
linked to:
IEEE 1149.1 JTAG boundary‑scan standard
|
| isPartOf | IEEE 1149 family of standards ⓘ |
| isUsedFor |
board-level production test
ⓘ
design-for-test (DFT) of high-speed digital systems ⓘ in-system test of high-speed interfaces ⓘ structural testing of printed circuit board interconnects ⓘ |
| publishedBy | Institute of Electrical and Electronics Engineers ⓘ |
| relatedTo |
IEEE 1149.10
ⓘ
IEEE 1149.4 ⓘ IEEE 1149.7 ⓘ |
| requires | IEEE 1149.1 compliant TAP controller ⓘ |
| supportsTestingOf |
AC-coupled interconnects
ⓘ
differential interconnects ⓘ gigabit serial links ⓘ high-speed digital interconnects ⓘ low-voltage differential signaling (LVDS) nets ⓘ |
| uses |
boundary-scan architecture
ⓘ
digital stimulus patterns adapted for AC coupling ⓘ edge-based detection for AC-coupled signals ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: IEEE 1149.6 Description of subject: IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
Referenced by (11)
Full triples — surface form annotated when it differs from this entity's canonical label.
subject linked to:
IEEE 1149.1 JTAG boundary‑scan standard
subject linked to:
IEEE 1149.1 JTAG boundary‑scan standard
linked to: IEEE 1149.6
linked to: IEEE 1149.6
linked to: IEEE 1149.6
linked to: IEEE 1149.6
linked to: IEEE 1149.6
linked to: IEEE 1149.6