IEEE 1500 embedded core test standard
E265710
The IEEE 1500 embedded core test standard defines a structured test access and wrapper architecture for testing individual IP cores within system-on-chip (SoC) designs.
All labels observed (3)
| Label | Occurrences |
|---|---|
| IEEE 1500 embedded core test standard canonical | 2 |
| IEEE Standard Testability Method for Embedded Core-based Integrated Circuits | 2 |
| IEEE 1500 core test standard | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T2424373 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: IEEE 1500 embedded core test standard Context triple: [IEEE 1149 family of standards, relatedTo, IEEE 1500 embedded core test standard]
-
A.
IEEE 1149 family of standards
The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
-
B.
IEEE 1149.10
IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.
-
C.
IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
-
D.
IEEE 1149.6
IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
-
E.
IEEE 1149.7
IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: IEEE 1500 embedded core test standard Target entity description: The IEEE 1500 embedded core test standard defines a structured test access and wrapper architecture for testing individual IP cores within system-on-chip (SoC) designs.
-
A.
IEEE 1149 family of standards
The IEEE 1149 family of standards is a set of Joint Test Action Group (JTAG) boundary-scan specifications that define methods for testing, debugging, and accessing digital integrated circuits and boards.
-
B.
IEEE 1149.10
IEEE 1149.10 is a JTAG-related IEEE standard that defines high-speed test access mechanisms for embedded instrumentation and system-level testing of complex digital devices and boards.
-
C.
IEEE 1149.1 JTAG boundary‑scan standard
The IEEE 1149.1 JTAG boundary-scan standard is a widely used test and debug specification that defines a serial interface and architecture for accessing and testing the internal logic and interconnects of integrated circuits and circuit boards.
-
D.
IEEE 1149.6
IEEE 1149.6 is a boundary-scan test standard that extends JTAG to support structural testing of high-speed AC-coupled and differential digital interconnects on printed circuit boards.
-
E.
IEEE 1149.7
IEEE 1149.7 is a compact, enhanced version of the JTAG test and debug standard that reduces pin count and power while adding advanced debug and trace capabilities for modern integrated circuits.
- F. None of above. chosen
Statements (45)
| Predicate | Object |
|---|---|
| instanceOf |
IEEE standard
ⓘ
technical standard ⓘ |
| alsoKnownAs |
IEEE 1500
ⓘ
IEEE 1500 core test standard ⓘ
linked to:
IEEE 1500 embedded core test standard
|
| appliesTo |
embedded cores
ⓘ
system-on-chip designs ⓘ |
| benefit |
enables scalable test architectures for large SoCs
ⓘ
improves test interoperability between IP providers and SoC integrators ⓘ reduces test integration effort for IP cores ⓘ |
| defines |
core test control protocol
ⓘ
core test wrapper architecture ⓘ test access mechanism interface ⓘ wrapper boundary register ⓘ wrapper data registers ⓘ wrapper instruction register ⓘ wrapper serial port ⓘ |
| field |
design for testability
ⓘ
integrated circuit testing ⓘ system-on-chip testing ⓘ |
| fullName |
IEEE Standard Testability Method for Embedded Core-based Integrated Circuits
ⓘ
linked to:
IEEE 1500 embedded core test standard
|
| goal |
to facilitate IP reuse with consistent testability features
ⓘ
to standardize embedded core test interfaces ⓘ |
| hasConcept |
external test mode
ⓘ
internal test mode ⓘ test access port at core level ⓘ wrapper bypass mode ⓘ wrapper input cells ⓘ wrapper output cells ⓘ |
| publishedBy |
IEEE Standards Association
ⓘ
Institute of Electrical and Electronics Engineers ⓘ |
| purpose |
to enable core-level test reuse
ⓘ
to isolate core tests from surrounding logic ⓘ to provide a standardized method for testing embedded IP cores in SoCs ⓘ to support plug-and-play integration of core test ⓘ |
| relatedTo |
IEEE 1149.1 boundary-scan standard
ⓘ
linked to:
IEEE 1149.1 JTAG boundary‑scan standard
IEEE 1687 embedded instrumentation standard ⓘ |
| scope |
core-level test access and wrapper definition
ⓘ
test control and data transport for embedded cores ⓘ |
| supports |
functional testing of embedded cores
ⓘ
hierarchical test access ⓘ structural testing of embedded cores ⓘ test pattern reuse across SoC designs ⓘ |
| usedIn |
IP core development
ⓘ
automatic test pattern generation flows ⓘ system-on-chip design flows ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: IEEE 1500 embedded core test standard Description of subject: The IEEE 1500 embedded core test standard defines a structured test access and wrapper architecture for testing individual IP cores within system-on-chip (SoC) designs.
Referenced by (5)
Full triples — surface form annotated when it differs from this entity's canonical label.
IEEE 1500 embedded core test standard
→
fullName
→
IEEE Standard Testability Method for Embedded Core-based Integrated Circuits
ⓘ
linked to: IEEE 1500 embedded core test standard
linked to: IEEE 1500 embedded core test standard
IEEE 1500
→
fullName
→
IEEE Standard Testability Method for Embedded Core-based Integrated Circuits
ⓘ
linked to: IEEE 1500 embedded core test standard