Harvard architecture
E87766
Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
All labels observed (6)
How this entity was disambiguated
This entity first appeared as the object of triple T737776 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Harvard architecture Context triple: [von Neumann architecture, contrastedWith, Harvard architecture]
-
A.
von Neumann architecture
The von Neumann architecture is a foundational computer design model in which a single memory stores both program instructions and data, executed sequentially by a central processing unit.
-
B.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
C.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
D.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
E.
SGI Altix ICE architecture
SGI Altix ICE architecture is a high-performance computing platform designed by Silicon Graphics for scalable, cluster-based supercomputers using industry-standard components and advanced interconnects.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: Harvard architecture Target entity description: Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
-
A.
von Neumann architecture
The von Neumann architecture is a foundational computer design model in which a single memory stores both program instructions and data, executed sequentially by a central processing unit.
-
B.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
C.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
-
D.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
E.
SGI Altix ICE architecture
SGI Altix ICE architecture is a high-performance computing platform designed by Silicon Graphics for scalable, cluster-based supercomputers using industry-standard components and advanced interconnects.
- F. None of above. chosen
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
computer architecture
ⓘ
instruction set architecture concept ⓘ |
| aimsTo | improve performance over unified-memory designs ⓘ |
| canBeImplementedAs |
modified Harvard architecture
ⓘ
strict Harvard architecture ⓘ |
| canImprove | throughput of pipelined processors ⓘ |
| canReduce | instruction fetch bottlenecks ⓘ |
| contrastsWith |
Princeton architecture
ⓘ
von Neumann architecture ⓘ |
| differsFrom |
von Neumann architecture in bus structure
ⓘ
von Neumann architecture in memory organization ⓘ |
| emergedIn | 1940s ⓘ |
| enables | simultaneous access to instructions and data ⓘ |
| hasAlternativeName |
Harvard computer architecture
ⓘ
linked to:
Harvard architecture
|
| hasLimitation |
more complex memory design than unified-memory systems
ⓘ
more complex programming model for self-modifying code ⓘ requires explicit mechanisms to write to instruction memory ⓘ |
| hasProperty |
can allow different access times for instructions and data
ⓘ
can allow different memory technologies for code and data ⓘ can allow different word widths for instructions and data ⓘ can fetch instructions and data in parallel ⓘ can simplify pipeline design ⓘ physically separate instruction and data memories ⓘ reduces contention between instruction fetch and data access ⓘ separate instruction and data buses ⓘ |
| historicallyAssociatedWith | Harvard Mark I computer ⓘ |
| influenced | modified Harvard architecture ⓘ |
| isBasisFor | modified Harvard architecture ⓘ |
| isCharacterizedBy |
no single shared bus for instructions and data
ⓘ
no single shared memory for instructions and data ⓘ |
| isCommonIn |
AVR microcontrollers
ⓘ
PIC microcontrollers ⓘ many DSP chips ⓘ |
| isDiscussedIn | computer architecture textbooks ⓘ |
| isNamedAfter | Harvard University ⓘ |
| isTaughtIn |
computer engineering curricula
ⓘ
computer science curricula ⓘ |
| isUsedIn |
digital signal processors
ⓘ
embedded systems ⓘ microcontrollers ⓘ some DSP-oriented CPUs ⓘ some RISC microcontrollers ⓘ |
| originatedAt | Harvard University ⓘ |
| supports | parallel instruction fetch and data access ⓘ |
| uses |
separate memory for data
ⓘ
separate memory for instructions ⓘ separate signal pathways for data ⓘ separate signal pathways for instructions ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: Harvard architecture Description of subject: Harvard architecture is a computer architecture design that uses separate memory and signal pathways for instructions and data, enabling simultaneous access and often improved performance over unified-memory designs.
Referenced by (12)
Full triples — surface form annotated when it differs from this entity's canonical label.
linked to: Harvard architecture
linked to: Harvard architecture
subject linked to:
Harvard Mark I computer
linked to: Harvard architecture
linked to: Harvard architecture
linked to: Harvard architecture
subject linked to:
Motorola 56001 DSP