von Neumann architecture

E14971

The von Neumann architecture is a foundational computer design model in which a single memory stores both program instructions and data, executed sequentially by a central processing unit.

AI illustration

How this image was made

AI-generated illustration of von Neumann architecture

This AI-generated illustration was produced by black-forest-labs/FLUX.2-dev (1024x1024) from a prompt written by openai/gpt-oss-120b from the entity's label + description.

Prompt

Generate an image of the von Neumann architecture (The von Neumann architecture is a foundational computer design model in which a single memory stores both program instructions and data, executed sequentially by a central processing unit.)

All labels observed (3)

How this entity was disambiguated

Statements (47)

Predicate Object
instanceOf computer architecture ⓘ
stored-program architecture ⓘ
appliedIn EDVAC ⓘ
IAS machine ⓘ
most personal computers ⓘ
most servers ⓘ
most workstations ⓘ
characterizedBy sequential processing ⓘ
shared bus for data and instructions ⓘ
stored-program concept ⓘ
von Neumann bottleneck ⓘ
contrastedWith Harvard architecture ⓘ
dateProposed 1945 ⓘ
documentedIn First Draft of a Report on the EDVAC ⓘ
enables programs as data ⓘ
self-modifying code ⓘ
hasComponent arithmetic logic unit ⓘ
central processing unit ⓘ
control unit ⓘ
input unit ⓘ
memory ⓘ
output unit ⓘ
hasGoal flexible general-purpose computation ⓘ
hasInfluenceOn CPU design ⓘ
computer organization textbooks ⓘ
memory hierarchy design ⓘ
programming language implementation ⓘ
hasLimitation instruction and data contention on same bus ⓘ
memory bandwidth bottleneck ⓘ
implementedBy general-purpose CPUs ⓘ
microprocessors ⓘ
influenced early electronic computers ⓘ
modern general-purpose computers ⓘ
namedAfter John von Neumann ⓘ
relatedTo control flow ⓘ
instruction set architecture ⓘ
stored-program computer ⓘ
stores data in memory ⓘ
program instructions in memory ⓘ
supports imperative programming languages ⓘ
sequential programming model ⓘ
uses binary representation of data ⓘ
fetch-decode-execute cycle ⓘ
program counter ⓘ
sequential instruction execution ⓘ
single address space for code and data ⓘ
single shared memory for instructions and data ⓘ

How these facts were elicited

Referenced by (17)

Full triples — surface form annotated when it differs from this entity's canonical label.

John von Neumann → knownFor → von Neumann architecture ⓘ
von Neumann architecture → characterizedBy → von Neumann bottleneck ⓘ
linked to: von Neumann architecture
First Draft of a Report on the EDVAC → influenced → von Neumann architecture ⓘ
IAS machine → architecture → von Neumann architecture ⓘ
EDVAC → influenced → von Neumann architecture ⓘ
von Neumann probe → relatedTo → von Neumann machine ⓘ
linked to: von Neumann architecture
John von Neumann → knownFor → von Neumann architecture ⓘ
subject linked to: Neumann
Princeton architecture → alternativeName → von Neumann architecture ⓘ
Princeton architecture → limitation → von Neumann bottleneck ⓘ
linked to: von Neumann architecture
ILLIAC I → architecture → von Neumann architecture ⓘ
SILLIAC → architecture → von Neumann architecture ⓘ
JOHNNIAC → architectureBasedOn → von Neumann architecture ⓘ
AVIDAC → architectureType → von Neumann architecture ⓘ
ARM7TDMI → hasFeature → von Neumann architecture ⓘ
Arithmetic logic unit → usedIn → von Neumann architecture ⓘ
EDSAC → architecture → von Neumann architecture ⓘ