AVX-512

E640424

AVX-512 is an advanced SIMD instruction set for x86 processors that enables high-throughput parallel processing using 512-bit wide vector operations.

All labels observed (15)

How this entity was disambiguated

Statements (72)

Predicate Object
instanceOf SIMD instruction set ⓘ
vector instruction set ⓘ
architectureFamily x86 ⓘ
backwardCompatibleWith AVX2 at instruction-set level ⓘ
bitWidth 512-bit ⓘ
comparedTo AVX2 ⓘ
linked to: Intel AVX2
detectableVia CPUID instruction ⓘ
enables high-throughput parallel processing ⓘ
processing of 16 32-bit integers per vector ⓘ
processing of 16 single-precision floats per vector ⓘ
processing of 32 16-bit integers per vector ⓘ
processing of 64 8-bit integers per vector ⓘ
processing of 8 64-bit integers per vector ⓘ
processing of 8 double-precision floats per vector ⓘ
extends AVX ⓘ
AVX2 ⓘ
linked to: Intel AVX2

SSE ⓘ
firstIntroducedInMicroarchitecture Intel Knights Landing ⓘ
Intel Skylake-X ⓘ
introducedBy Intel ⓘ
linked to: Intel Corporation
mayBeDisabledBy BIOS settings ⓘ
mayBeDisabledBy microcode updates ⓘ
opmaskRegisterCount 8 ⓘ
opmaskRegisterWidth 64-bit ⓘ
optimizationConcern higher power consumption ⓘ
thermal throttling risk ⓘ
provides mask-based predication not in AVX2 ⓘ
more registers than AVX2 ⓘ
wider vectors than AVX2 ⓘ
registerWidth 512-bit ZMM registers ⓘ
requires hardware support in CPU ⓘ
subset AVX-5124FMAPS ⓘ
linked to: AVX-512

AVX-5124VNNIW ⓘ
AVX-512BF16 ⓘ
linked to: AVX-512

AVX-512BITALG ⓘ
linked to: AVX-512

AVX-512BW ⓘ
AVX-512DQ ⓘ
AVX-512ER ⓘ
linked to: AVX-512

AVX-512F ⓘ
linked to: AVX-512

AVX-512IFMA ⓘ
linked to: AVX-512

AVX-512PF ⓘ
linked to: AVX-512

AVX-512VBMI ⓘ
linked to: AVX-512

AVX-512VL ⓘ
linked to: AVX-512

AVX-512VNNI ⓘ
linked to: AVX-512

AVX-512VP2INTERSECT ⓘ
subset AVX-512CD ⓘ
linked to: AVX-512
supports bitwise operations ⓘ
conflict detection instructions ⓘ
expansion and compression of vectors ⓘ
floating-point vector operations ⓘ
fused multiply-add ⓘ
gather operations ⓘ
integer vector operations ⓘ
mask registers ⓘ
mask-based blending ⓘ
per-lane predication ⓘ
permutation instructions ⓘ
scatter operations ⓘ
vector operations ⓘ
vector reductions ⓘ
targetUseCase data analytics ⓘ
high-performance computing ⓘ
machine learning workloads ⓘ
scientific computing ⓘ
signal processing ⓘ
usedIn Intel Core X-series processors ⓘ
Intel Xeon Scalable processors ⓘ
linked to: Intel Xeon

some Intel client CPUs ⓘ
usesRegisterType XMM registers ⓘ
YMM registers ⓘ
ZMM registers ⓘ
opmask registers ⓘ

How these facts were elicited

Referenced by (23)

Full triples — surface form annotated when it differs from this entity's canonical label.

x86 → hasExtension → AVX-512 ⓘ
Intel AVX2 → precedes → Intel AVX-512 ⓘ
linked to: AVX-512
Intel AVX → successor → Intel AVX-512 ⓘ
linked to: AVX-512
Intel AVX → relatedStandard → Intel AVX-512 ⓘ
linked to: AVX-512
Tiger Lake → supports → AVX-512 ⓘ
subject linked to: Tiger Lake microarchitecture
Intel Fortran Compiler → optimizedFor → Intel AVX-512 instruction set ⓘ
linked to: AVX-512
AVX → successor → AVX-512 ⓘ
AVX-512 → subset → AVX-512F ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-512CD ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-512VL ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-512IFMA ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-512VBMI ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-512VNNI ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-512BF16 ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-512BITALG ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-512ER ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-512PF ⓘ
linked to: AVX-512
AVX-512 → subset → AVX-5124FMAPS ⓘ
linked to: AVX-512
Intel SHA Extensions → relatedTo → Intel AVX-512 ⓘ
linked to: AVX-512
Zen 4 → supports → AVX-512 (subset, on some implementations) ⓘ
linked to: AVX-512
Willow Cove → supports → Intel AVX-512 ⓘ
linked to: AVX-512