POWER Architecture, first generation

E758591

POWER Architecture, first generation refers to IBM’s original POWER1 RISC microprocessor design that formed the basis for the later POWER and PowerPC processor families.

All labels observed (2)

How this entity was disambiguated

Statements (47)

Predicate Object
instanceOf IBM POWER architecture generation ⓘ
RISC architecture ⓘ
microprocessor architecture ⓘ
alsoKnownAs POWER1 architecture ⓘ
linked to: POWER1
ancestorOf POWER3 architecture ⓘ
linked to: IBM POWER3 family

POWER4 architecture ⓘ
modern IBM POWER processors ⓘ
basedOn IBM 801 project ⓘ
IBM America Project ⓘ
commercializationEra early 1990s ⓘ
designedFor high-performance UNIX systems ⓘ
designGoal high floating-point performance ⓘ
scalability for servers and workstations ⓘ
developer IBM ⓘ
endianSupport big-endian ⓘ
hasFeature branch processing unit ⓘ
fixed-length instructions ⓘ
load-store architecture ⓘ
pipelined execution units ⓘ
register-to-register operations ⓘ
separate integer and floating-point units ⓘ
hasRegisterType condition register ⓘ
count register ⓘ
floating-point registers ⓘ
general-purpose registers ⓘ
link register ⓘ
influenced PowerPC instruction set architecture ⓘ
linked to: PowerPC

later POWER2 design ⓘ
instructionSetType reduced instruction set computing ⓘ
introducedBy IBM RS/6000 workstations ⓘ
linked to: IBM RS/6000 systems
introducedInProductLine IBM RS/6000 servers ⓘ
linked to: IBM RS/6000 systems
marketedFor enterprise servers ⓘ
technical workstations ⓘ
partOfFamily IBM POWER architecture family ⓘ
primaryVendor IBM ⓘ
runsOperatingSystem AIX ⓘ
successor POWER Architecture, second generation ⓘ
PowerPC architecture ⓘ
linked to: PowerPC
supports branch prediction ⓘ
floating-point operations ⓘ
integer operations ⓘ
out-of-order execution (at implementation level in POWER1) ⓘ
superscalar execution ⓘ
usedIn IBM POWER1 microprocessor ⓘ
linked to: IBM POWER1

IBM POWER1+ microprocessor ⓘ
linked to: IBM POWER1

early IBM RS/6000 models ⓘ
wordSize 32-bit ⓘ

How these facts were elicited

Referenced by (2)

Full triples — surface form annotated when it differs from this entity's canonical label.

POWER1 → alsoKnownAs → POWER Architecture, first generation ⓘ
POWER Architecture, first generation → successor → POWER Architecture, second generation ⓘ
linked to: POWER Architecture, first generation