Nios II
E724162
Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
All labels observed (4)
| Label | Occurrences |
|---|---|
| Nios II canonical | 4 |
| Nios II soft processor | 2 |
| Nios | 1 |
| Nios II/e (economy) configuration | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T8285570 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Nios II Context triple: [QEMU, supportsGuestArchitecture, Nios II]
-
A.
Tensilica Xtensa LX6
Tensilica Xtensa LX6 is a customizable 32-bit RISC processor core widely used in embedded systems for its efficient performance and low power consumption, notably in Espressif’s ESP32 SoCs.
-
B.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
C.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
D.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
E.
RISC II
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: Nios II Target entity description: Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
-
A.
Tensilica Xtensa LX6
Tensilica Xtensa LX6 is a customizable 32-bit RISC processor core widely used in embedded systems for its efficient performance and low power consumption, notably in Espressif’s ESP32 SoCs.
-
B.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
C.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
-
D.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
E.
RISC II
RISC II is an early experimental reduced instruction set computer (RISC) processor developed at UC Berkeley that significantly shaped the design of later RISC architectures.
- F. None of above. chosen
Statements (50)
| Predicate | Object |
|---|---|
| instanceOf |
32-bit RISC processor
ⓘ
embedded processor core ⓘ soft-core processor architecture ⓘ |
| architectureType | RISC ⓘ |
| bitWidth | 32-bit ⓘ |
| category |
FPGA IP core
ⓘ
soft microprocessor core ⓘ |
| designedFor | customizable embedded systems on FPGAs ⓘ |
| developer |
Altera
ⓘ
Intel ⓘ
linked to:
Intel Corporation
|
| documentationPublisher |
Intel PSG (Programmable Solutions Group)
ⓘ
linked to:
Intel PSG
|
| ecosystem |
HAL (Hardware Abstraction Layer) libraries
ⓘ
RTOS support from multiple vendors ⓘ |
| feature |
configurable pipeline depth and performance levels
ⓘ
high-performance configuration for larger FPGAs ⓘ small footprint configuration for low-cost FPGAs ⓘ |
| hasVariant |
Nios II/e (economy) configuration
ⓘ
linked to:
Nios II
Nios II/f (fast) configuration ⓘ Nios II/s (standard) configuration ⓘ |
| implementationType | soft-core ⓘ |
| intendedPlatform | FPGA ⓘ |
| introducedBy | Altera ⓘ |
| market |
communications equipment
ⓘ
embedded systems ⓘ industrial control ⓘ |
| ownedBy |
Intel
ⓘ
linked to:
Intel Corporation
|
| predecessor | Nios ⓘ |
| programmingLanguageSupport |
C
ⓘ
C++ ⓘ |
| supports |
Harvard architecture style instruction and data paths
ⓘ
MMU-less configurations ⓘ configurable cache sizes ⓘ configurable memory interfaces ⓘ custom instructions ⓘ debug via JTAG ⓘ exceptions ⓘ hardware acceleration via custom logic ⓘ interrupts ⓘ off-chip memory interfaces ⓘ on-chip debug modules ⓘ on-chip memory ⓘ optional memory management features ⓘ |
| toolchain |
GCC-based compiler support
ⓘ
Intel Quartus Prime integration ⓘ Platform Designer (Qsys) integration ⓘ |
| typicalUseCase |
embedded control in FPGA-based systems
ⓘ
signal processing on FPGA ⓘ system-on-a-programmable-chip designs ⓘ |
| usedWith |
Altera FPGA devices
ⓘ
linked to:
Altera
Intel FPGA devices ⓘ
linked to:
FPGA
|
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: Nios II Description of subject: Nios II is a soft-core 32-bit RISC processor architecture developed by Altera (now Intel) for implementation on FPGA devices.
Referenced by (8)
Full triples — surface form annotated when it differs from this entity's canonical label.
linked to: Nios II
linked to: Nios II
linked to: Nios II
linked to: Nios II