ARMv5 architecture
E358144
ARMv5 architecture is a 32-bit RISC processor architecture from ARM that introduced enhancements over earlier ARM generations, including support for more advanced instruction sets and extensions used in many embedded and mobile devices.
All labels observed (7)
| Label | Occurrences |
|---|---|
| ARMv5 architecture family | 2 |
| ARMv5 | 1 |
| ARMv5 architecture canonical | 1 |
| ARMv5T | 1 |
| ARMv5TE | 1 |
| ARMv5TE architecture | 1 |
| ARMv5TEJ | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T3421602 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: ARMv5 architecture Context triple: [VFP floating-point extension, targetPlatform, ARMv5 architecture]
-
A.
ARMv6 architecture family
The ARMv6 architecture family is a generation of 32-bit ARM processor designs that introduced significant enhancements in performance, multimedia processing, and security features for mobile and embedded devices.
-
B.
ARMv7-A architecture
ARMv7-A architecture is a 32-bit ARM processor architecture widely used in smartphones, tablets, and embedded systems, featuring advanced performance, virtualization, and security capabilities.
-
C.
ARM
ARM is a family of energy-efficient RISC processor architectures widely used in mobile devices, embedded systems, and increasingly in laptops and servers.
-
D.
ARMv9-A
ARMv9-A is a modern 64-bit ARM architecture generation that introduces enhanced performance, security, and AI-focused features for advanced processors used in devices like Apple’s M-series chips.
-
E.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: ARMv5 architecture Target entity description: ARMv5 architecture is a 32-bit RISC processor architecture from ARM that introduced enhancements over earlier ARM generations, including support for more advanced instruction sets and extensions used in many embedded and mobile devices.
-
A.
ARMv6 architecture family
The ARMv6 architecture family is a generation of 32-bit ARM processor designs that introduced significant enhancements in performance, multimedia processing, and security features for mobile and embedded devices.
-
B.
ARMv7-A architecture
ARMv7-A architecture is a 32-bit ARM processor architecture widely used in smartphones, tablets, and embedded systems, featuring advanced performance, virtualization, and security capabilities.
-
C.
ARM
ARM is a family of energy-efficient RISC processor architectures widely used in mobile devices, embedded systems, and increasingly in laptops and servers.
-
D.
ARMv9-A
ARMv9-A is a modern 64-bit ARM architecture generation that introduces enhanced performance, security, and AI-focused features for advanced processors used in devices like Apple’s M-series chips.
-
E.
Acorn RISC Machine
Acorn RISC Machine (ARM) is a family of energy-efficient reduced instruction set computer (RISC) architectures widely used in mobile devices, embedded systems, and increasingly in servers and personal computers.
- F. None of above. chosen
Statements (49)
| Predicate | Object |
|---|---|
| instanceOf |
32-bit RISC architecture
ⓘ
ARM architecture family member ⓘ instruction set architecture ⓘ |
| addressSpace | 32-bit linear address space ⓘ |
| addsFeature |
DSP-enhanced instruction set (E extension)
ⓘ
Jazelle Java bytecode execution (J extension) ⓘ enhanced multiply and multiply-accumulate operations ⓘ improved exception handling ⓘ saturating arithmetic for DSP ⓘ |
| addsOver |
ARMv4T
ⓘ
linked to:
ARMv4
|
| architectureStyle | RISC ⓘ |
| backwardCompatibleWith |
ARMv4T
ⓘ
linked to:
ARMv4
|
| bitWidth | 32-bit ⓘ |
| codeDensity | improved via Thumb support ⓘ |
| developer |
ARM Limited
ⓘ
linked to:
Arm Ltd.
|
| endianSupport |
bi-endian
ⓘ
little-endian ⓘ |
| includesVersion |
ARMv5T
ⓘ
linked to:
ARMv5 architecture
ARMv5TE ⓘ
linked to:
ARMv5 architecture
ARMv5TEJ ⓘ
linked to:
ARMv5 architecture
|
| introduced | late 1990s ⓘ |
| marketRole | mainstream embedded architecture in early 2000s ⓘ |
| powerEfficiency | optimized for low power consumption ⓘ |
| predecessor | ARMv4 ⓘ |
| registerFile | 16 general-purpose registers (architected) ⓘ |
| successor |
ARMv6
ⓘ
linked to:
ARMv6 architecture family
|
| supports |
ARM instruction set
ⓘ
linked to:
ARM
Jazelle DBX ⓘ Thumb instruction set ⓘ clz (count leading zeros) instruction ⓘ conditional execution of most instructions ⓘ enhanced DSP instructions ⓘ enhanced multiply-accumulate instructions ⓘ saturating arithmetic instructions ⓘ |
| supportsOperatingSystem |
Linux
ⓘ
Windows CE ⓘ
linked to:
Windows Embedded family
various real-time operating systems ⓘ |
| targetDomain |
consumer electronics
ⓘ
embedded systems ⓘ mobile devices ⓘ networking equipment ⓘ |
| usedIn |
ARM10 processor family
ⓘ
ARM9 processor family ⓘ
linked to:
ARM9
XScale processors ⓘ
linked to:
Intel XScale
many system-on-chip designs ⓘ |
| uses |
16-bit Thumb instruction encoding
ⓘ
fixed 32-bit ARM instruction encoding ⓘ load-store architecture ⓘ |
| wordSize | 32 bits ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: ARMv5 architecture Description of subject: ARMv5 architecture is a 32-bit RISC processor architecture from ARM that introduced enhancements over earlier ARM generations, including support for more advanced instruction sets and extensions used in many embedded and mobile devices.
Referenced by (8)
Full triples — surface form annotated when it differs from this entity's canonical label.
linked to: ARMv5 architecture
linked to: ARMv5 architecture
linked to: ARMv5 architecture
subject linked to:
ARMv5 architecture
linked to: ARMv5 architecture
subject linked to:
ARMv5 architecture
linked to: ARMv5 architecture
subject linked to:
ARMv5 architecture
linked to: ARMv5 architecture