Verilog

E237419
HDL IEEE standard hardware description language programming language

Verilog is a hardware description language (HDL) used to model, design, and verify digital circuits and systems such as those implemented in CPLDs and FPGAs.

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All labels observed (5)

Label Occurrences
Verilog canonical 26
Verilog HDL 1
Verilog-1995 1

How this entity was disambiguated

Statements (70)

Predicate Object
instanceOf HDL ⓘ
IEEE standard ⓘ
hardware description language ⓘ
programming language ⓘ
category textual HDL ⓘ
commonlyUsedWith ASIC design flow ⓘ
FPGA toolchain ⓘ
HDL simulator ⓘ
logic synthesizer ⓘ
competesWith VHDL ⓘ
designAbstractionLevel behavioral ⓘ
gate level ⓘ
register-transfer level ⓘ
executionModel simulation-based ⓘ
field computer engineering ⓘ
digital design ⓘ
electronic design automation ⓘ
firstStandardizedIn 1995 ⓘ
hasConcept always block ⓘ
function ⓘ
generate block ⓘ
initial block ⓘ
module ⓘ
reg ⓘ
system function ⓘ
system task ⓘ
task ⓘ
timescale directive ⓘ
wire ⓘ
hasFileExtension .v ⓘ
.vh ⓘ
hasVersion Verilog-1995 ⓘ
linked to: Verilog

Verilog-2001 ⓘ
linked to: Verilog

Verilog-2005 ⓘ
linked to: Verilog
influenced Bluespec SystemVerilog ⓘ
Chisel ⓘ
SystemVerilog ⓘ
Verilog-AMS ⓘ
influencedBy C programming language ⓘ
linked to: C

hardware description languages ⓘ
standardizedBy IEEE ⓘ
linked to: Institute of Electrical and Electronics Engineers
standardNumber IEEE 1364 ⓘ
status largely subsumed by SystemVerilog for new designs ⓘ
supports bit-level operations ⓘ
blocking assignments ⓘ
concurrent execution ⓘ
continuous assignments ⓘ
event-driven simulation ⓘ
module hierarchy ⓘ
non-blocking assignments ⓘ
parameterization ⓘ
procedural blocks ⓘ
synthesis constructs ⓘ
testbench constructs ⓘ
timing control ⓘ
typicalTarget ASIC ⓘ
CPLD ⓘ
linked to: CPLDs

FPGA ⓘ
usedFor ASIC design ⓘ
CPLD design ⓘ
FPGA design ⓘ
behavioral modeling ⓘ
designing digital circuits ⓘ
gate-level modeling ⓘ
modeling digital circuits ⓘ
register-transfer level design ⓘ
simulation of digital systems ⓘ
synthesis of digital hardware ⓘ
testbench creation ⓘ
verifying digital circuits ⓘ

How these facts were elicited

Referenced by (30)

Full triples — surface form annotated when it differs from this entity's canonical label.

CPLD → configuredBy → Verilog ⓘ
subject linked to: CPLDs
VLSI technology → usesLanguage → Verilog ⓘ
Mentor Graphics → languageSupport → Verilog ⓘ
FPGA → uses → Verilog ⓘ
Quartus design software → supportsLanguage → Verilog ⓘ
MAX+PLUS II → supportsLanguage → Verilog ⓘ
Cyclone → supports → Verilog ⓘ
VHDL → competesWith → Verilog ⓘ
Verilog → hasVersion → Verilog-1995 ⓘ
linked to: Verilog
Verilog → hasVersion → Verilog-2001 ⓘ
linked to: Verilog
Verilog → hasVersion → Verilog-2005 ⓘ
linked to: Verilog
Clang-Format → supportsLanguage → Verilog ⓘ
SystemVerilog → basedOn → Verilog ⓘ
ModelSim → supportsLanguage → Verilog ⓘ
Questa → supportsLanguage → Verilog ⓘ
Cyclone III → supportsLanguage → Verilog ⓘ
Pro Edition → supports → Verilog HDL ⓘ
linked to: Verilog
Altera Hardware Description Language → competesWith → Verilog ⓘ
IEEE 1364 → defines → Verilog ⓘ
Verilog-AMS → basedOn → Verilog ⓘ
Verilog-AMS → hasSyntaxSimilarityWith → Verilog ⓘ
Chisel → outputFormat → Verilog ⓘ
Chisel → comparedTo → Verilog ⓘ
Bluespec SystemVerilog → basedOn → Verilog ⓘ
Bluespec SystemVerilog → extends → Verilog ⓘ
Bluespec SystemVerilog → relatedTo → Verilog ⓘ
ASIC → commonHDL → Verilog ⓘ
Vivado Design Suite → supportsLanguage → Verilog ⓘ
ISE Design Suite → supportsLanguage → Verilog ⓘ
Spartan FPGA family → supports → Verilog ⓘ