SSSE3
E167944
SSSE3 (Supplemental Streaming SIMD Extensions 3) is an Intel SIMD instruction set extension that enhances performance for multimedia, signal processing, and other parallelizable workloads.
All labels observed (2)
| Label | Occurrences |
|---|---|
| SSSE3 canonical | 11 |
| Supplemental Streaming SIMD Extensions 3 | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T1429502 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: SSSE3 Context triple: [Intel Atom, supports, SSSE3]
-
A.
SSE3
SSE3 (Streaming SIMD Extensions 3) is an Intel CPU instruction set extension that adds additional SIMD operations to improve performance in multimedia, gaming, and scientific applications.
-
B.
SSE2
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
-
C.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
D.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: SSSE3 Target entity description: SSSE3 (Supplemental Streaming SIMD Extensions 3) is an Intel SIMD instruction set extension that enhances performance for multimedia, signal processing, and other parallelizable workloads.
-
A.
SSE3
SSE3 (Streaming SIMD Extensions 3) is an Intel CPU instruction set extension that adds additional SIMD operations to improve performance in multimedia, gaming, and scientific applications.
-
B.
SSE2
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
-
C.
Intel AVX2
Intel AVX2 is an x86 instruction set extension from Intel that enhances performance for integer-heavy and vectorized workloads through wider SIMD operations and new vector instructions.
-
D.
Intel AVX
Intel AVX is an x86 processor instruction set extension from Intel that accelerates floating-point and vector-intensive workloads, commonly used in high-performance computing, multimedia, and scientific applications.
-
E.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
- F. None of above. chosen
Statements (46)
| Predicate | Object |
|---|---|
| instanceOf |
SIMD instruction set extension
ⓘ
x86 instruction set extension ⓘ |
| abbreviation | SSSE3 ⓘ |
| architecture |
x86
ⓘ
x86-64 ⓘ |
| backwardCompatible | true ⓘ |
| bitWidth | 128 bits ⓘ |
| category |
SIMD extension for x86
ⓘ
vector instruction set ⓘ |
| compatibleWith |
SSE
ⓘ
SSE2 ⓘ SSE3 ⓘ |
| containsInstructionType |
absolute value operations on packed integers
ⓘ
aligned and unaligned packed moves with duplication ⓘ byte-wise shuffle operations ⓘ horizontal add and subtract operations ⓘ multiply-add operations on packed integers ⓘ sign-extended packed multiply operations ⓘ |
| definedIn | Intel 64 and IA-32 Architectures Software Developer’s Manual ⓘ |
| designedFor | parallelizable workloads ⓘ |
| extends | SSE3 ⓘ |
| firstSupportedMicroarchitecture | Intel Core microarchitecture ⓘ |
| firstSupportedProcessorFamily |
Intel Core 2
ⓘ
Intel Xeon (Core-based) ⓘ
linked to:
Intel Xeon
|
| fullName |
Supplemental Streaming SIMD Extensions 3
ⓘ
linked to:
SSSE3
|
| improves |
performance of SIMD integer arithmetic
ⓘ
performance of dot-product-like operations ⓘ performance of packed data rearrangement ⓘ |
| introducedBy |
Intel
ⓘ
linked to:
Intel Corporation
|
| predecessor | SSE3 ⓘ |
| primaryUse |
cryptography acceleration
ⓘ
general-purpose data-parallel workloads ⓘ image processing ⓘ multimedia processing ⓘ signal processing ⓘ video processing ⓘ |
| registerFileUsed | XMM registers ⓘ |
| requiresFeatureFlag | SSSE3 CPUID feature bit ⓘ |
| successor |
SSE4.1
ⓘ
SSE4.2 ⓘ |
| supportsDataType |
128-bit SIMD integer vectors
ⓘ
packed 16-bit integers ⓘ packed 32-bit integers ⓘ packed 64-bit integers ⓘ packed 8-bit integers ⓘ |
| yearIntroduced | 2006 ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: SSSE3 Description of subject: SSSE3 (Supplemental Streaming SIMD Extensions 3) is an Intel SIMD instruction set extension that enhances performance for multimedia, signal processing, and other parallelizable workloads.
Referenced by (12)
Full triples — surface form annotated when it differs from this entity's canonical label.