SSE2
E163309
SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
All labels observed (4)
| Label | Occurrences |
|---|---|
| SSE2 canonical | 21 |
| MMX | 1 |
| SSE (on later IA-32 CPUs) | 1 |
| SSE2 floating-point | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T1429500 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: SSE2 Context triple: [Intel Atom, supports, SSE2]
-
A.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
-
B.
AMD64 architecture
The AMD64 architecture is a 64-bit instruction set architecture introduced by AMD that extends the x86 design to support larger memory addressing and enhanced performance while maintaining backward compatibility with 32-bit software.
-
C.
Intel Xeon
Intel Xeon is a family of high-performance x86 processors designed by Intel for servers, workstations, and data center applications requiring reliability, scalability, and advanced multi-core processing.
-
D.
AMD processors
AMD processors are a family of CPUs and APUs from Advanced Micro Devices known for offering strong multi-core performance and competitive pricing across desktops, laptops, and mobile devices.
-
E.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: SSE2 Target entity description: SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
-
A.
AltiVec
AltiVec is a vector processing extension for the PowerPC architecture that accelerates multimedia, signal processing, and other parallelizable computations.
-
B.
AMD64 architecture
The AMD64 architecture is a 64-bit instruction set architecture introduced by AMD that extends the x86 design to support larger memory addressing and enhanced performance while maintaining backward compatibility with 32-bit software.
-
C.
Intel Xeon
Intel Xeon is a family of high-performance x86 processors designed by Intel for servers, workstations, and data center applications requiring reliability, scalability, and advanced multi-core processing.
-
D.
AMD processors
AMD processors are a family of CPUs and APUs from Advanced Micro Devices known for offering strong multi-core performance and competitive pricing across desktops, laptops, and mobile devices.
-
E.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
- F. None of above. chosen
Statements (48)
| Predicate | Object |
|---|---|
| instanceOf |
SIMD instruction set
ⓘ
instruction set extension ⓘ x86 extension ⓘ |
| addsCapability |
128-bit SIMD registers usage for integers
ⓘ
advanced SIMD operations ⓘ integer SIMD operations ⓘ packed double-precision floating-point operations ⓘ |
| architecture |
IA-32
ⓘ
x86 ⓘ x86-64 ⓘ |
| compatibleWith |
AMD processors
ⓘ
Intel processors ⓘ |
| enables | vectorization by compilers ⓘ |
| extends |
MMX
ⓘ
SSE ⓘ |
| firstImplementedBy |
Intel Pentium 4 microarchitecture
ⓘ
linked to:
Pentium 4
|
| firstImplementedIn | Pentium 4 ⓘ |
| improves |
encryption performance
ⓘ
floating-point performance ⓘ integer performance ⓘ multimedia processing ⓘ scientific computing ⓘ |
| introducedBy |
Intel
ⓘ
linked to:
Intel Corporation
|
| mandatoryIn | x86-64 architecture ⓘ |
| predecessor | SSE ⓘ |
| registerWidth | 128-bit ⓘ |
| replaces | x87 FPU for many floating-point operations ⓘ |
| requiredBy |
AMD64 specification
ⓘ
linked to:
AMD64 architecture
|
| standardizedIn | Intel Architecture Software Developer’s Manual ⓘ |
| successor | SSE3 ⓘ |
| supportsDataType |
64-bit integer operations in SIMD
ⓘ
double-precision floating-point ⓘ packed integers ⓘ |
| supportsOperation |
conversion between integer and floating-point types
ⓘ
data movement instructions ⓘ packed add ⓘ packed comparisons ⓘ packed logical operations ⓘ packed multiply ⓘ packed shifts ⓘ packed subtract ⓘ |
| usedFor |
3D graphics
ⓘ
audio processing ⓘ cryptography ⓘ signal processing ⓘ video encoding ⓘ |
| usesRegisters | XMM registers ⓘ |
| yearIntroduced | 2001 ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: SSE2 Description of subject: SSE2 is an x86 processor instruction set extension introduced by Intel that adds advanced SIMD (Single Instruction, Multiple Data) capabilities for faster floating-point and integer computations.
Referenced by (24)
Full triples — surface form annotated when it differs from this entity's canonical label.
linked to: SSE2
linked to: SSE2
linked to: SSE2