cacheType
P9924
predicate
Indicates the specific kind or category of cache associated with an entity or operation.
All labels observed (5)
| Label | Occurrences |
|---|---|
| cacheType canonical | 60 |
| cache | 9 |
| cacheSupport | 8 |
| cacheFeature | 2 |
| cacheOrganization | 2 |
Description generation (PDg)
The one-sentence description above was generated by prompting gpt-5.1 with the predicate name and this instruction.
Instruction
Given a predicate that represents a relationship or action between entities, generate a one-sentence description explaining its meaning. # Instructions Focus on describing the relationship, not the entities themselves. # Response Format Begin the description with \' Indicates...\'
Input
Predicate: cacheType
Generated description
Indicates the specific kind or category of cache associated with an entity or operation.
Sample triples (81)
| Subject | Object |
|---|---|
| ARP | dynamic ARP entry ⓘ |
| ARP | static ARP entry ⓘ |
| Intel Pentium | 8 KB instruction cache via predicate surface "cache" ⓘ |
| Intel Pentium | 8 KB data cache via predicate surface "cache" ⓘ |
| Firestorm | L1 instruction cache ⓘ |
| Firestorm | L1 data cache ⓘ |
| Firestorm | L2 cache ⓘ |
| PowerPC G4 | on-chip L1 cache ⓘ |
| PowerPC G4 | external or on-chip L2 cache ⓘ |
| Intel Core Solo | L2 cache ⓘ |
| Intel 80486 | on-chip L1 cache ⓘ |
| Gracemont | shared L2 per cluster ⓘ |
| Intel Core m3-8100Y | Intel Smart Cache ⓘ |
| PowerPC G3 | on-chip L1 cache ⓘ |
| Alpha architecture | on-chip caches via predicate surface "cacheSupport" ⓘ |
| PowerPC G5 | L1 instruction cache ⓘ |
| PowerPC G5 | L1 data cache ⓘ |
| PowerPC G5 | L2 cache ⓘ |
| POWER2 | external L2 cache ⓘ |
| POWER2 | separate instruction and data cache support via predicate surface "cacheOrganization" ⓘ |
| PowerPC 603 | separate instruction and data caches ⓘ |
| PowerPC 604 | separate instruction and data caches ⓘ |
| Crusoe microprocessor | on-chip L1 cache via predicate surface "cacheFeature" ⓘ |
| Crusoe microprocessor | on-chip L2 cache in some models via predicate surface "cacheFeature" ⓘ |
| Phenom | shared L3 cache ⓘ |
| Motorola 68060 | separate instruction and data caches ⓘ |
| UltraSPARC T3 | L1 instruction cache ⓘ |
| UltraSPARC T3 | L1 data cache ⓘ |
| UltraSPARC T3 | shared L2 cache ⓘ |
| UltraSPARC II | on-chip instruction cache ⓘ |
| UltraSPARC II | on-chip data cache ⓘ |
| UltraSPARC III | on-chip L1 cache ⓘ |
| UltraSPARC III | external L2 cache ⓘ |
| UltraSPARC T5 | L1 cache ⓘ |
| UltraSPARC T5 | L2 cache ⓘ |
| UltraSPARC T5 | L3 cache ⓘ |
| DEC Alpha 21164 | split L1 instruction and data caches ⓘ |
|
NEC VR4300
linked to:
64-bit NEC VR4300
|
instruction cache via predicate surface "cache" ⓘ |
|
NEC VR4300
linked to:
64-bit NEC VR4300
|
data cache via predicate surface "cache" ⓘ |
| MIPS R4600 | separate instruction and data caches ⓘ |
| MIPS R4600 | write-back cache via predicate surface "cacheOrganization" ⓘ |
| MIPS R5000 | on-chip instruction cache via predicate surface "cacheSupport" ⓘ |
| MIPS R5000 | on-chip data cache via predicate surface "cacheSupport" ⓘ |
| ARM9 | instruction cache (in many ARM9 cores) via predicate surface "cacheSupport" ⓘ |
| ARM9 | data cache (in many ARM9 cores) via predicate surface "cacheSupport" ⓘ |
| Yonah | shared L2 cache ⓘ |
| Intel Pentium M | L1 cache ⓘ |
| Intel Pentium M | L2 cache ⓘ |
| Intel Core Duo | L2 cache ⓘ |
| Morgan | on-die L2 cache ⓘ |