Symbolic Model Checking

E239161

formal verification technique model checking technique

Symbolic Model Checking is a formal verification technique that uses symbolic representations, such as binary decision diagrams, to efficiently verify properties of hardware and software systems with very large state spaces.

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All labels observed (4)

Label	Occurrences
Symbolic Model Checking: An Approach to the State Explosion Problem	4
Symbolic Model Checking canonical	1
Symbolic Model Checking (paper)	1
Symbolic Model Checking: 10^20 States and Beyond	1

How this entity was disambiguated

This entity first appeared as the object of triple T2169590 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.

NED1 Entity disambiguation (via context triple) gpt-5-mini-2025-08-07

Target entity: Symbolic Model Checking
Context triple: [Edmund M. Clarke, notableWork, Symbolic Model Checking]

A. Temporal Logic of Actions
Temporal Logic of Actions is a formal framework for specifying and reasoning about concurrent and distributed systems using temporal logic to describe system behaviors over time.
B. CCS (Calculus of Communicating Systems)
CCS (Calculus of Communicating Systems) is a formal process calculus introduced by Robin Milner for modeling, specifying, and reasoning about concurrent, communicating systems in computer science.
C. Isabelle/HOL: A Proof Assistant for Higher-Order Logic
"Isabelle/HOL: A Proof Assistant for Higher-Order Logic" is a foundational book and system documentation that presents the Isabelle/HOL interactive theorem prover, widely used for formal verification and higher-order logic reasoning in computer science and mathematics.
D. Hoare logic
Hoare logic is a formal system in computer science used to reason rigorously about the correctness of computer programs using logical assertions about program states.
E. A Symbolic Analysis of Relay and Switching Circuits
A Symbolic Analysis of Relay and Switching Circuits is Claude Shannon’s landmark 1937 master’s thesis that founded modern digital circuit design by applying Boolean algebra to relay and switching systems.
F. None of above. chosen
G. Unsure - the case is ambiguous/there is not enough information to decide.

NED2 Entity disambiguation (via description) gpt-5-mini-2025-08-07

Target entity: Symbolic Model Checking
Target entity description: Symbolic Model Checking is a formal verification technique that uses symbolic representations, such as binary decision diagrams, to efficiently verify properties of hardware and software systems with very large state spaces.

A. Temporal Logic of Actions
Temporal Logic of Actions is a formal framework for specifying and reasoning about concurrent and distributed systems using temporal logic to describe system behaviors over time.
B. CCS (Calculus of Communicating Systems)
CCS (Calculus of Communicating Systems) is a formal process calculus introduced by Robin Milner for modeling, specifying, and reasoning about concurrent, communicating systems in computer science.
C. Isabelle/HOL: A Proof Assistant for Higher-Order Logic
"Isabelle/HOL: A Proof Assistant for Higher-Order Logic" is a foundational book and system documentation that presents the Isabelle/HOL interactive theorem prover, widely used for formal verification and higher-order logic reasoning in computer science and mathematics.
D. Hoare logic
Hoare logic is a formal system in computer science used to reason rigorously about the correctness of computer programs using logical assertions about program states.
E. A Symbolic Analysis of Relay and Switching Circuits
A Symbolic Analysis of Relay and Switching Circuits is Claude Shannon’s landmark 1937 master’s thesis that founded modern digital circuit design by applying Boolean algebra to relay and switching systems.
F. None of above. chosen

Statements (51)

Predicate	Object
instanceOf	formal verification technique ⓘ model checking technique ⓘ
addresses	state space explosion problem ⓘ
aimsTo	verify properties of hardware systems ⓘ verify properties of software systems ⓘ
associatedWithInstitution	Carnegie Mellon University ⓘ linked to: CMU
associatedWithResearcher	E. Allen Emerson ⓘ Edmund M. Clarke ⓘ Kenneth L. McMillan ⓘ
checksPropertyType	fairness properties ⓘ liveness properties ⓘ safety properties ⓘ
comparedTo	explicit-state model checking ⓘ
coreConcept	symbolic encoding of state sets as Boolean formulas ⓘ symbolic encoding of transition relations as Boolean formulas ⓘ
hasAdvantage	can handle extremely large state spaces compactly ⓘ often more memory-efficient than explicit-state methods ⓘ
hasLimitation	BDD size can blow up for some systems ⓘ performance depends on variable ordering ⓘ
inspired	development of SAT-based model checking ⓘ
introducedIn	late 1980s ⓘ
notablePublication	Symbolic Model Checking: 10^20 States and Beyond ⓘ linked to: Symbolic Model Checking
operatesOn	very large state spaces ⓘ
relatedTechnique	SAT-based model checking ⓘ SMT-based model checking ⓘ bounded model checking ⓘ
represents	sets of states symbolically ⓘ transition relations symbolically ⓘ
supportsLogic	CTL ⓘ LTL ⓘ temporal logic ⓘ µ-calculus ⓘ
usedInDomain	embedded systems verification ⓘ hardware verification ⓘ protocol verification ⓘ
usedInTool	Cadence SMV ⓘ NuSMV ⓘ SMV ⓘ
usesAlgorithmicTechnique	backward reachability ⓘ fixed-point computation ⓘ forward reachability ⓘ reachability analysis ⓘ
usesDataStructure	OBDDs ⓘ ordered binary decision diagrams ⓘ
usesRepresentation	BDDs ⓘ binary decision diagrams ⓘ symbolic representation ⓘ
verificationTarget	communication protocols ⓘ concurrent software ⓘ finite-state systems ⓘ synchronous hardware circuits ⓘ

How these facts were elicited