POWER instruction set architecture
E216082
The POWER instruction set architecture is a reduced instruction set computing (RISC) architecture originally developed by IBM for high-performance servers and workstations, forming the basis for later PowerPC and Power Architecture designs.
All labels observed (4)
| Label | Occurrences |
|---|---|
| POWER ISA | 8 |
| POWER architecture | 4 |
| POWER instruction set architecture canonical | 1 |
| Power Architecture ISA | 1 |
How this entity was disambiguated
This entity first appeared as the object of triple T1937003 — resolving that mention is where its identity was fixed. The disambiguator weighed these candidate entities and picked the highlighted one (or “None”, minting a new entity). This is how homonymy is resolved: the same surface form can point to different entities.
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: POWER instruction set architecture Context triple: [Power Architecture, basedOn, POWER instruction set architecture]
-
A.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
B.
Independent Computing Architecture
Independent Computing Architecture (ICA) is Citrix's proprietary protocol for delivering virtual applications and desktops over a network, enabling remote access to centralized computing resources.
-
C.
Computer Architecture: Concepts and Evolution
"Computer Architecture: Concepts and Evolution" is a comprehensive reference book that traces the historical development and fundamental principles of computer architecture, co-authored by Gerrit Blaauw and Frederick Brooks.
-
D.
Xe-HPG microarchitecture
Xe-HPG microarchitecture is Intel’s high-performance gaming-oriented GPU architecture designed to power its discrete Arc graphics cards with advanced features like hardware-accelerated ray tracing.
-
E.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: POWER instruction set architecture Target entity description: The POWER instruction set architecture is a reduced instruction set computing (RISC) architecture originally developed by IBM for high-performance servers and workstations, forming the basis for later PowerPC and Power Architecture designs.
-
A.
SPARC microprocessor architecture
The SPARC microprocessor architecture is a RISC-based instruction set architecture widely used in high-performance and enterprise servers, originally created to power scalable, multi-processor systems.
-
B.
Independent Computing Architecture
Independent Computing Architecture (ICA) is Citrix's proprietary protocol for delivering virtual applications and desktops over a network, enabling remote access to centralized computing resources.
-
C.
Computer Architecture: Concepts and Evolution
"Computer Architecture: Concepts and Evolution" is a comprehensive reference book that traces the historical development and fundamental principles of computer architecture, co-authored by Gerrit Blaauw and Frederick Brooks.
-
D.
Xe-HPG microarchitecture
Xe-HPG microarchitecture is Intel’s high-performance gaming-oriented GPU architecture designed to power its discrete Arc graphics cards with advanced features like hardware-accelerated ray tracing.
-
E.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
- F. None of above. chosen
Statements (41)
| Predicate | Object |
|---|---|
| instanceOf |
RISC architecture
ⓘ
instruction set architecture ⓘ |
| architectureFamily | POWER ⓘ |
| category |
IBM instruction set architectures
ⓘ
RISC instruction set architectures ⓘ |
| computingParadigm | reduced instruction set computing ⓘ |
| countryOfOrigin |
United States
ⓘ
linked to:
United States of America
|
| designedFor |
IBM RS/6000 servers
ⓘ
linked to:
IBM RS/6000 systems
IBM RS/6000 workstations ⓘ
linked to:
IBM RS/6000 systems
|
| developer | IBM ⓘ |
| formsBasisOf |
Power Architecture
ⓘ
PowerPC ⓘ |
| hasAbbreviation |
POWER ISA
ⓘ
linked to:
POWER instruction set architecture
|
| hasDesignGoal |
high performance
ⓘ
scalability ⓘ support for multiprocessing ⓘ |
| hasFeature |
condition register
ⓘ
fixed-length instructions ⓘ large register file ⓘ separate integer and floating-point registers ⓘ support for out-of-order execution in implementations ⓘ support for pipelining ⓘ |
| influenced |
Power Architecture specification
ⓘ
linked to:
Power Architecture
PowerPC instruction set architecture ⓘ
linked to:
PowerPC
|
| introducedBy |
IBM RS/6000 line
ⓘ
linked to:
IBM RS/6000 systems
|
| marketedBy | IBM ⓘ |
| relatedTo |
Power Architecture
ⓘ
PowerPC architecture ⓘ
linked to:
PowerPC
|
| successor |
Power Architecture ISA
ⓘ
linked to:
POWER instruction set architecture
PowerPC instruction set architecture ⓘ
linked to:
PowerPC
|
| supports |
32-bit implementation
ⓘ
branch instructions ⓘ floating-point operations ⓘ integer operations ⓘ load-store architecture ⓘ superscalar implementation ⓘ |
| usedFor |
high-performance servers
ⓘ
workstations ⓘ |
| usedIn |
IBM POWER1 processors
ⓘ
linked to:
IBM POWER instruction set
IBM POWER2 processors ⓘ IBM RS/6000 systems ⓘ |
How these facts were elicited
The pipeline generated the facts above by prompting gpt-5.1 with this entity's name + description and the instruction below.
Instruction
You are a knowledge base construction expert. Given a subject entity and a description of it, return factual statements that you know for the subject as a JSON list of dictionaries(triples), where keys must be "subject", "predicate" and "object". The number of facts may be very high, between 25 to 50 or more, for very popular subjects. For less popular subjects, the number of facts can be very low, like 5 or 10. # Requirements - If you don't know the subject at all, return an empty list. - If the subject is not a named entity, return an empty list. - Include at least one triple where predicate is "instanceOf". - Do not get too wordy. - Separate several objects into multiple triples with one object.
Input
Subject: POWER instruction set architecture Description of subject: The POWER instruction set architecture is a reduced instruction set computing (RISC) architecture originally developed by IBM for high-performance servers and workstations, forming the basis for later PowerPC and Power Architecture designs.
Referenced by (14)
Full triples — surface form annotated when it differs from this entity's canonical label.
linked to: POWER instruction set architecture
linked to: POWER instruction set architecture
linked to: POWER instruction set architecture
linked to: POWER instruction set architecture
linked to: POWER instruction set architecture
linked to: POWER instruction set architecture
linked to: POWER instruction set architecture
linked to: POWER instruction set architecture
linked to: POWER instruction set architecture
linked to: POWER instruction set architecture
subject linked to:
POWER2 RISC processor
linked to: POWER instruction set architecture