Triple
T9176160
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Book III |
E220202
|
entity |
| Predicate | isPartOfStandard |
P7659
|
FINISHED |
| Object | Power ISA documentation set |
E41463
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Power ISA documentation set | Statement: [Book III, isPartOfStandard, Power ISA documentation set]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: Power ISA documentation set Context triple: [Book III, isPartOfStandard, Power ISA documentation set]
-
A.
Power ISA
chosen
Power ISA is IBM's modern 64-bit RISC instruction set architecture used in high-performance servers, embedded systems, and supercomputers, evolving from the earlier PowerPC architecture.
-
B.
Intel Architecture Software Developer’s Manual
The Intel Architecture Software Developer’s Manual is Intel’s comprehensive technical reference that defines and documents the x86/x86-64 instruction set architecture, processor features, and programming guidelines for software and systems developers.
-
C.
IBM POWER instruction set
The IBM POWER instruction set is a RISC-based computer architecture developed by IBM for its high-performance POWER processors used in servers, workstations, and supercomputers.
-
D.
POWER instruction set architecture
The POWER instruction set architecture is a reduced instruction set computing (RISC) architecture originally developed by IBM for high-performance servers and workstations, forming the basis for later PowerPC and Power Architecture designs.
-
E.
MIPS
MIPS is a RISC (Reduced Instruction Set Computer) processor architecture widely used in embedded systems, networking equipment, and academic settings.
- F. None of above.
- G. Unsure - the case is ambiguous/there is not enough information to decide.
Provenance (3 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ca83e589948190ac9907819db11ddf |
completed | March 30, 2026, 2:08 p.m. |
| NER | Named-entity recognition | batch_69ccbfa496548190a096969eebf732f3 |
completed | April 1, 2026, 6:48 a.m. |
| NED1 | Entity disambiguation (via context triple) | batch_69d054a87f3881908bda69238d2b97ab |
completed | April 4, 2026, midnight |
Created at: March 30, 2026, 7:23 p.m.