Triple

T31583658
Position Surface form Disambiguated ID Type / Status
Subject Nova 16-bit minicomputers E805890 entity
Predicate primaryBusWidth P178344 FINISHED
Object 16-bit LITERAL FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: 16-bit | Statement: [Nova 16-bit minicomputers, primaryBusWidth, 16-bit]
PD Predicate disambiguation gpt-5-mini-2025-08-07
Target predicate: primaryBusWidth
Context triple: [Nova 16-bit minicomputers, primaryBusWidth, 16-bit]
  • A. memoryBusWidthBits chosen
    Indicates the width, in bits, of the data path used by the memory bus to transfer information.
  • B. busWidthComparedToISA
    Indicates how the width of a bus compares to the width defined by a given instruction set architecture (ISA), such as being wider, narrower, or equal.
  • C. supportsMemoryBusWidth
    Indicates that one entity is compatible with or able to operate using the specified memory bus width of another entity.
  • D. bitWidth
    Indicates the number of bits used to represent or encode a given value, type, or data element.
  • E. hasBusArchitecture
    Indicates that one entity uses, implements, or is characterized by a particular bus architecture in its design or operation.
  • F. None of above.

Provenance (3 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69f348d3a86c8190a3e5e539a4dd125f completed April 30, 2026, 12:19 p.m.
NER Named-entity recognition batch_6a037c876524819098545e6037d3107d completed May 12, 2026, 7:16 p.m.
PD Predicate disambiguation batch_6a0379e7aa0c8190bdc9ee4d54fc821b completed May 12, 2026, 7:05 p.m.
Created at: April 30, 2026, 10:24 p.m.