Triple

T27657967
Position Surface form Disambiguated ID Type / Status
Subject Q-bus E697042 entity
Predicate hasAdvantageOver P635 FINISHED
Object Unibus in wiring complexity reduction
Unibus in wiring complexity reduction is a computer bus architecture designed to simplify system interconnections by consolidating multiple signal pathways into a single shared communication channel, thereby reducing the amount and complexity of wiring needed.
E1782955 NE FINISHED

How this triple was built (2 steps)

Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.

NER Named-entity recognition gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Unibus in wiring complexity reduction | Statement: [Q-bus, hasAdvantageOver, Unibus in wiring complexity reduction]
NEDg Description generation gpt-5.1
Instruction
Generate a one-sentence description of the target entity. 
You are given a context triple in the form (subject, predicate, object), where the object is the target entity. 
# Instructions
Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. 
Avoid repeating the information from the triple, unless really essential.
# Response Format
Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Unibus in wiring complexity reduction
Triple: [Q-bus, hasAdvantageOver, Unibus in wiring complexity reduction]
Generated description
Unibus in wiring complexity reduction is a computer bus architecture designed to simplify system interconnections by consolidating multiple signal pathways into a single shared communication channel, thereby reducing the amount and complexity of wiring needed.

Provenance (5 batches)

The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.

Step Stage Batch ID Status When
creating Elicitation batch_69ef590b85a4819083ec7c12bd3c9c10 completed April 27, 2026, 12:39 p.m.
NER Named-entity recognition batch_69f631dad37c8190ab1b5918ad8a928a completed May 2, 2026, 5:18 p.m.
NED1 Entity disambiguation (via context triple) batch_6a12da9c5f3881909282cfb27a2c4624 completed May 24, 2026, 11:01 a.m.
NEDg Description generation batch_6a12dba401e081909133c45b038798e5 completed May 24, 2026, 11:06 a.m.
NED2 Entity disambiguation (via description) batch_6a12dc0d6f8881908c158355b595139c completed May 24, 2026, 11:07 a.m.
Created at: April 27, 2026, 2:35 p.m.