Triple
T26176644
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Zilog |
E654560
|
entity |
| Predicate | product |
P490
|
FINISHED |
| Object |
Zilog Z16 microcontroller family
The Zilog Z16 microcontroller family is a line of 16-bit embedded processors designed by Zilog for control-oriented applications requiring integrated peripherals and efficient real-time performance.
|
E1715907
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Zilog Z16 microcontroller family | Statement: [Zilog, product, Zilog Z16 microcontroller family]
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Zilog Z16 microcontroller family Triple: [Zilog, product, Zilog Z16 microcontroller family]
Generated description
The Zilog Z16 microcontroller family is a line of 16-bit embedded processors designed by Zilog for control-oriented applications requiring integrated peripherals and efficient real-time performance.
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69ee5b45873c81909499203612d05d07 |
completed | April 26, 2026, 6:36 p.m. |
| NER | Named-entity recognition | batch_69f60c6c9b808190812dcb252b9844f2 |
completed | May 2, 2026, 2:38 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_6a1185743a3081909531ca905478877b |
completed | May 23, 2026, 10:46 a.m. |
| NEDg | Description generation | batch_6a11868d16508190ae8827d4b07f0192 |
completed | May 23, 2026, 10:50 a.m. |
| NED2 | Entity disambiguation (via description) | batch_6a11876410f4819091b6b45abd657f54 |
completed | May 23, 2026, 10:54 a.m. |
Created at: April 26, 2026, 8:38 p.m.