Triple
T25425620
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Intel Architecture Software Developer’s Manual |
E637108
|
entity |
| Predicate | documents |
P450
|
FINISHED |
| Object |
Intel memory management features
Intel memory management features are the hardware and architectural mechanisms in Intel processors that control how memory is addressed, protected, translated, and optimized for performance in modern computing systems.
|
E1678940
|
NE FINISHED |
How this triple was built (2 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: Intel memory management features | Statement: [Intel Architecture Software Developer’s Manual, documents, Intel memory management features]
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: Intel memory management features Triple: [Intel Architecture Software Developer’s Manual, documents, Intel memory management features]
Generated description
Intel memory management features are the hardware and architectural mechanisms in Intel processors that control how memory is addressed, protected, translated, and optimized for performance in modern computing systems.
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e75db58a1c8190891b9ff7c2f8414e |
completed | April 21, 2026, 11:21 a.m. |
| NER | Named-entity recognition | batch_69f5f6bfdb748190abfd40ed1838d9aa |
completed | May 2, 2026, 1:06 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_6a10899c570881908096628a9552cef9 |
completed | May 22, 2026, 4:51 p.m. |
| NEDg | Description generation | batch_6a108a66ebfc8190843d591e9ab47493 |
completed | May 22, 2026, 4:55 p.m. |
| NED2 | Entity disambiguation (via description) | batch_6a108b1c1e888190b3fe80f1da6a4be5 |
completed | May 22, 2026, 4:58 p.m. |
Created at: April 21, 2026, 1:57 p.m.