Triple
T20399636
| Position | Surface form | Disambiguated ID | Type / Status |
|---|---|---|---|
| Subject | Indigo R3000 models |
E500296
|
entity |
| Predicate | processorFamily |
P11217
|
FINISHED |
| Object |
MIPS R3000
The MIPS R3000 is a 32-bit RISC microprocessor widely used in late-1980s and early-1990s workstations, servers, and embedded systems.
|
E1433476
|
NE FINISHED |
How this triple was built (4 steps)
Every LLM step that produced this triple, in pipeline order — named-entity classification, the disambiguation choices (the exact options shown, with the pick highlighted), and the generated description. The batch + timestamp of each is in the Provenance table below.
NER
Named-entity recognition
gpt-5-mini
Instruction
Given a phrase, classify it is english named entity (e.g., persons, organizations, works of art) in Latin script, or not (e.g., literals, dates, URLs, verbose phrases). For disambiguation, the statement where the phrase occurs as object is also given. Please return a JSON object with `phrase` (string, the phrase being analyzed) and `is_ne` (boolean, indicating whether the phrase is a Named Entity).
Input
Phrase: MIPS R3000 | Statement: [Indigo R3000 models, processorFamily, MIPS R3000]
NED1
Entity disambiguation (via context triple)
gpt-5-mini-2025-08-07
Target entity: MIPS R3000 Context triple: [Indigo R3000 models, processorFamily, MIPS R3000]
-
A.
MIPS R2000
The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
-
B.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
C.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
D.
Risc PC
Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
-
E.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
- F. None of above. chosen
- G. Unsure - the case is ambiguous/there is not enough information to decide.
NEDg
Description generation
gpt-5.1
Instruction
Generate a one-sentence description of the target entity. You are given a context triple in the form (subject, predicate, object), where the object is the target entity. # Instructions Use the triple to infer relevant information about the entity. Describe the entity based on what is most defining, well-known. Avoid repeating the information from the triple, unless really essential. # Response Format Return only the sentence: "Description: [one-sentence description of the target entity]"
Input
Entity: MIPS R3000 Triple: [Indigo R3000 models, processorFamily, MIPS R3000]
Generated description
The MIPS R3000 is a 32-bit RISC microprocessor widely used in late-1980s and early-1990s workstations, servers, and embedded systems.
NED2
Entity disambiguation (via description)
gpt-5-mini-2025-08-07
Target entity: MIPS R3000 Target entity description: The MIPS R3000 is a 32-bit RISC microprocessor widely used in late-1980s and early-1990s workstations, servers, and embedded systems.
-
A.
MIPS R2000
The MIPS R2000 is an early 32-bit RISC microprocessor that helped popularize the MIPS architecture in academic and commercial systems during the late 1980s.
-
B.
MIPS R5000
The MIPS R5000 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
C.
MIPS R4600
The MIPS R4600 is a 64-bit RISC microprocessor from the MIPS family, widely used in mid-1990s workstations and embedded systems for its balance of performance and cost.
-
D.
Risc PC
Risc PC is a modular personal computer introduced by Acorn Computers in the 1990s, known for its RISC-based architecture and expandability.
-
E.
MIPS II
MIPS II is the second-generation version of the MIPS instruction set architecture, extending the original design with additional instructions and features for improved performance and functionality.
- F. None of above. chosen
Provenance (5 batches)
The batch behind each pipeline step, in order, with when it ran. Timestamps are batch-level — stages were processed in waves, so the object chain (NER → NED1 → NEDg → NED2) reads in order, but predicate / elicitation batches can sit in a different wave.
| Step | Stage | Batch ID | Status | When |
|---|---|---|---|---|
| creating | Elicitation | batch_69e0b4a81bec8190b69adfdc1336a015 |
completed | April 16, 2026, 10:06 a.m. |
| NER | Named-entity recognition | batch_69e6798cf04481909f183c4c75fe6d52 |
completed | April 20, 2026, 7:07 p.m. |
| NED1 | Entity disambiguation (via context triple) | batch_6a088b03a3fc8190974a8558ba974ce9 |
completed | May 16, 2026, 3:19 p.m. |
| NEDg | Description generation | batch_6a088ee32484819083761c12c2696d7e |
completed | May 16, 2026, 3:36 p.m. |
| NED2 | Entity disambiguation (via description) | batch_6a088f7669088190962837848103d0de |
completed | May 16, 2026, 3:38 p.m. |
Created at: April 16, 2026, 11:29 a.m.