L1Cache
P53883
predicate
Indicates a relationship where data or instructions are stored or accessed in the first-level (closest, fastest) cache memory associated with a processor core.
All labels observed (8)
| Label | Occurrences |
|---|---|
| L1CacheSize | 21 |
| L1Cache canonical | 9 |
| L1DataCacheSize | 5 |
| L1InstructionCacheSize | 5 |
| onChipCache | 5 |
| hasL1Cache | 3 |
| l1Cache | 2 |
| l1CacheType | 1 |
Description generation (PDg)
The one-sentence description above was generated by prompting gpt-5.1 with the predicate name and this instruction.
Instruction
Given a predicate that represents a relationship or action between entities, generate a one-sentence description explaining its meaning. # Instructions Focus on describing the relationship, not the entities themselves. # Response Format Begin the description with \' Indicates...\'
Input
Predicate: L1Cache
Generated description
Indicates a relationship where data or instructions are stored or accessed in the first-level (closest, fastest) cache memory associated with a processor core.
Sample triples (51)
| Subject | Object |
|---|---|
| RAD750 | 32 KB instruction cache ⓘ |
| RAD750 | 32 KB data cache ⓘ |
| Airmont | 32 KB instruction cache per core via predicate surface "l1Cache" ⓘ |
| Airmont | 24 KB data cache per core via predicate surface "l1Cache" ⓘ |
| Intel Pentium Pro | 8 KB data cache via predicate surface "L1CacheSize" ⓘ |
| Intel Pentium Pro | 8 KB instruction cache via predicate surface "L1CacheSize" ⓘ |
| P54C | unified L1 cache via predicate surface "l1CacheType" ⓘ |
| AMD Duron | 128 KB via predicate surface "L1CacheSize" ⓘ |
| AMD Duron | 64 KB via predicate surface "L1DataCacheSize" ⓘ |
| AMD Duron | 64 KB via predicate surface "L1InstructionCacheSize" ⓘ |
| PowerPC G3 | 32 KB instruction cache via predicate surface "L1CacheSize" ⓘ |
| PowerPC G3 | 32 KB data cache via predicate surface "L1CacheSize" ⓘ |
|
Motorola 68040
linked to:
Motorola 68040 microprocessor
|
separate instruction and data caches via predicate surface "onChipCache" ⓘ |
| PowerPC 601 | 32 KB unified ⓘ |
| PowerPC 603 | 8 KB via predicate surface "L1InstructionCacheSize" ⓘ |
| PowerPC 603 | 8 KB via predicate surface "L1DataCacheSize" ⓘ |
| PowerPC 604 | instruction cache ⓘ |
| PowerPC 604 | data cache ⓘ |
| DEC Alpha 21264 | 64 KB instruction cache ⓘ |
| DEC Alpha 21264 | 64 KB data cache ⓘ |
| DEC Alpha 21164 | instruction cache via predicate surface "onChipCache" ⓘ |
| DEC Alpha 21164 | data cache via predicate surface "onChipCache" ⓘ |
| DEC Alpha 21164 | secondary cache via predicate surface "onChipCache" ⓘ |
| Apple A5 | yes via predicate surface "hasL1Cache" ⓘ |
| Intel Pentium II | 32 KB via predicate surface "L1CacheSize" ⓘ |
| Intel Pentium 75 | 8 KB instruction cache via predicate surface "L1CacheSize" ⓘ |
| Intel Pentium 75 | 8 KB data cache via predicate surface "L1CacheSize" ⓘ |
| Intel Pentium 90 | 8 KB instruction cache via predicate surface "L1CacheSize" ⓘ |
| Intel Pentium 90 | 8 KB data cache via predicate surface "L1CacheSize" ⓘ |
| Intel Pentium 100 | 16 KB via predicate surface "L1CacheSize" ⓘ |
| Intel Pentium 100 | 8 KB via predicate surface "L1InstructionCacheSize" ⓘ |
| Intel Pentium 100 | 8 KB via predicate surface "L1DataCacheSize" ⓘ |
| Duron | 128 KB via predicate surface "L1CacheSize" ⓘ |
| AMD K6-2 | 32 KB instruction cache via predicate surface "L1CacheSize" ⓘ |
| AMD K6-2 | 32 KB data cache via predicate surface "L1CacheSize" ⓘ |
| Morgan | 128 KB via predicate surface "L1CacheSize" ⓘ |
| Morgan | 64 KB via predicate surface "L1DataCacheSize" ⓘ |
| Morgan | 64 KB via predicate surface "L1InstructionCacheSize" ⓘ |
| Intel Pentium 120 | yes via predicate surface "hasL1Cache" ⓘ |
| Intel Pentium 133 | 16 KB via predicate surface "L1CacheSize" ⓘ |
| Morgan | 64 KB instruction cache ⓘ |
| Morgan | 64 KB data cache ⓘ |
| AMD 486 | 8 KB via predicate surface "L1CacheSize" ⓘ |
| AMD 486 | 16 KB via predicate surface "L1CacheSize" ⓘ |
| Barton | 128 KB via predicate surface "L1CacheSize" ⓘ |
| Barton | 64 KB via predicate surface "L1DataCacheSize" ⓘ |
| Barton | 64 KB via predicate surface "L1InstructionCacheSize" ⓘ |
| POWER8 | per-core instruction and data caches via predicate surface "hasL1Cache" ⓘ |
| IBM Gekko | 32 KB instruction cache via predicate surface "L1CacheSize" ⓘ |
| IBM Gekko | 32 KB data cache via predicate surface "L1CacheSize" ⓘ |